Faculty

Bing Sheu Honorary Chair Professor
photo
Position
Honorary Chair Professor
Education
Ph.D. in Electrical Engineering, University of California, Berkeley, 1985 
E-mail
bjsheu@tsmc.com ; b.sheu@ieee.org
Room
Office hour
Telephone
FAX
Homepage
Laboratory
Major Field
Course

Record
2007.04
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迄今 Program Leader, Talents Track, National Science and Technology Program for System-on-Chip (NSoC) Office, Apr. 2007 – present
2007
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迄今 Honorary Chair Professor, National Chiao Tung University, since 2007.
2007
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迄今 Honorary Chair Professor, National Chiao Tung University, since 2007.
2006.08
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迄今 Director, R&D Design and Technology Platform, Taiwan Semiconductor Manufacturing Company (TSMC), Aug. 2006 – present.
2006.05
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迄今 Chair of Globalization Competitiveness Advisory Board, EE Dept., National Cheng Kung University (NCKU), appointed in May 2006.
2005.05
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2006.07 R&D Director, fastSPICE at Analog Mixed-Signal Division, under Silicon Engineering Group Business Unit, Synopsys Corporation, May 2005 –July 2006.
2004.06
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迄今 (International) Chair Professor, National Chiao Tung University, since June 2004.
2004.05
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2004.07 國立交通大學電機資訊學院代理副院長(2004年5月21日~7月31日)
2004
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迄今 國立交通大學(院長級)校務策略顧問(2004~)
2003.02
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2003.07 Adjunct Professor, EE Dept. National Chiao Tung University, Feb. – July 2003.
2003
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迄今 Honorary Professor, National Chiao Tung University, Awarded July 2003.
2002.10
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2005.05 Senior Director of Technology Partnerships and Device Modeling, Nassda Corp., May 2004 – May 2005; Director, Oct. 2002 – Apr. 2004.
2002
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2006 Advisory-Board Member, EECS College, National Chiao Tung University, 2002 – 2006.
2001
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2002 • Product Specialist/Developer, Device Modeling Manager (Oct. 2001-2002) & Product Manuals Manger (since April 2002-Oct. 2002
2000
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2001 國際電機電子學會 電路與系統學術會 總裁(2000)、資深總裁(2001)
1999
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2000 Device Modeling Head, Avant! Corporation (merged into Synopsys Corporation in June 2002), Jan. 1999 – April 2000.
1999
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1999 多媒体期刊 創刊總編輯(1999)
1998
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1998 • Visiting Professor, EE Dept. National Chiao Tung University, and Institute of Information Sciences at Academia Sinica, Fall 1998 semester.
1998
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1999 國際電機電子學會 電路與系統學術會 副總裁(1998)、備位總裁(1999)
1997.01
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1997.12 Director, VLSI Multimedia Laboratory, Jan. – Dec. 1997.
1997
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迄今 國立台灣大學電機工程研究所榮譽顧問(1997)
1997
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迄今 國立成功大學電腦系統研發中心榮譽顧問(1997)
1997
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1998 Tenured Professor (1997-98), Biomedical Engineering Dept., University of Southern California.
1997
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1998 Tenured Professor (1997-98),Electrical Engineering Dept., University of Southern California.
1997
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迄今 國立成功大學電腦系統研發中心榮譽顧問(1997)
1997
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1997 國立台灣大學電機工程研究所榮譽顧問(1997)
1997
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1998 Editor-in-Chief, IEEE Transactions on VLSI Systems, 1997-1998.
1995.07
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1998.05 Co-Director, VLSI Design MSEE Program, July 1995 - May 1998.
1994.01
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1996.12 Director, VLSI Signal Processing Laboratory, Jan. 1994- Dec. 1996.
1993.04
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1995.06 Associate Director, VLSI Design MSEE Program, April 1993- June 1995.
1993
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1998 Associate Director, VLSI Design MSEE Program, April 1993- June 1995. Co-Director, VLSI Design MSEE Program, July 1995 - May 1998.
1985
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1991 Assistant Professor (1985-91), Electrical Engineering Dept., University of Southern California.
1982
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1985 Research Assistant, Electronics Research Lab., U.C. Berkeley, 1982-1985.
1981
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1982 Teaching Assistant, EECS Dept., U.C. Berkeley, 1981-1982.
Honor & Awards
2006
Outstanding Education Contributions Award, Ministry of Education, Taiwan Government, Sept. 2006.
2004
Meritorious Service Award, IEEE Circuits and Systems Society, May 2004.
2004
Appreciation Award plaque (as EIC of T-VLSI in 1997-98), jointly from IEEE Computer Society, IEEE Solid-State Circuits Society, IEEE Circuits and Systems Society, March 2004.
2002
Appreciation Award plaque, IEEE Circuits and Devices Magazine (based on Award from Society of Technical Communications), Nov. 2002.
1999
Golden Jubilee Award, IEEE Circuits and Systems Society, 1999.
1998
Fulbright Senior Scholarship Award, U.S. Information Agency, 1998.
1998
Fulbright Senior Scholarship Award, U.S. Information Agency, 1998.
1997
IEEE Guillemin-Cauer Award, Best Paper of Transactions on Circuits and Systems, 1997.
1996
Fellow Award, IEEE, Jan. 1996.
1995
Best Paper Award, IEEE Transactions on VLSI Systems, 1995.
1991
Best Presenter Award, Design & Test Track, IEEE International Conference on Computer Design, 1991.
1990
Best Presenter Award, Architecture & Algorithms Track, IEEE International Conference on Computer Design, 1990.
1987
Engineering Initiation Award, National Science Foundation, 1987.
1981
Stanley M. Tasheria Scholarship, U.C. Berkeley, 1981.
1980
Tse-Wei Liu Memorial Fellowship, U.C. Berkeley, 1980.
1978
Distinguished Student (Book Coupon) Award (7 times), National Taiwan University, 1978.

Research

Research Achievement
Journal
[1] B. J. Sheu, C.-Y. Wu, S. Sze, Scanning the Issue, Nanoelectronics and Nanoscale Processing Special Issue, Proceedings of IEEE, vol. 91, no. 11, pp. 1747 – 1752, Nov. 2003.
[2] T. W. Berger, M. Baudry, R. D. Brinton, J.-S. Liaw, V. Marmarelis, A. Y. Park, B. J. Sheu, A. R. Tanguay, “Brain-Implantable Biomimetic Electronics as the Next Era in Neural Prosthetics,” Proceedings of IEEE, vol. 89, no. 7, pp. 993-1012, July 2001.
[3] S. H. Jen, B. J. Sheu, Y. Park, ”A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC’s,” IEEE Jour. of Solid-State Circuits, vol. 34, no. 1, pp. 103-106, Jan. 1999.
[4] S. H. Jen, C. C. Enz, D. R. Pehlke, M. Schroder, B. J. Sheu, ”Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz, ” IEEE Trans. on Electron Devices, vol. 46, no. 11, pp 2217-2227, Nov. 1999.
[5] R. H. Tsai, B. J. Sheu, T. W. Berger, "A VLSI Neural Network Processor Based on Hippocampal Model," Jour. of Analog ICs & Signal Processing, Kluwer Academic Publishers, vol. 15, pp. 201-203, 1998.
[6] M. Wang, B. J. Sheu, T. Berger, E. Y. Chou, A. K. Cho, "Architecture and design of 1-D enhanced cellular neural network processors for signal detection," J. of Analog ICs & Signal Processing, Kluwer Academic Publishers, vol. 15, pp. 201-213, 1998.
[7] S. H. Jen, B. J. Sheu, "A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs," IEEE Trans. on Computer-Aided Design, vol. 17, no. 2, pp. 169-172, Feb. 1998.
[8] D. C. Chen, B. J. Sheu, "A compact neural network based CDMA receiver," IEEE Trans. on Circuits and Systems, Part II, vol. 45, no. 3, pp. 384-387, Mar. 1998.
[9] E. Y. Chou, B. J. Sheu, M. Wang, "A compact neural network for VLSI PRML detectors: scalable architecture," IEEE Trans. on Circuits and Systems II, vol. 45, no. 6, pp. 709-719, June 1998.
[10] E. Y. Chou, B. J. Sheu, M. Wang, "A compact neural network for partial-response maximum-likehood detectors: algorithmic study," IEEE Trans. on Circuits and Systems II, vol. 45, no. 7, pp. 848-856, July 1998.
[11] E. Y. Chou, B. J. Sheu, R. C. Chang, "VLSI design of optimization and image processing cellular neural networks," IEEE Trans. on Circuits and Systems I, vol. 44, no. 1, pp. 12-20, Jan. 1997.
[12] S. Jen, B. J. Sheu, "A unified approach to submicron DC MOS transistor modeling for low-voltage ICs," Jour. of Analog ICs & Signal Processing, Kluwer Academic Publishers, vol. 12, pp. 107-118, 1997.
[13] E. Y. Chou, B. J. Sheu, R. H. Tsai, "A state-constrained model for cellular nonlinear network optimization," IEEE Trans. on Circuits and Systems I, vol. 44, no. 5, pp. 445-449, May 1997.
[14] D. C. Chen, B. J. Sheu, W. C. Young, "A CDMA communication detector with robust near-far resistance using paralleled array processors," IEEE Trans. on Circuits & Systems for Video Technology, vol 7, no. 4, pp. 654-662, Aug. 1997.
[15] R. H. Tsai, B. J. Sheu, A. Kostrzewski, J. Kim, "Advanced in efficient optical links to enhance desktop multimedia processor systems," IEEE Trans. on Circuits & Systems for Video Technology, vol 7, no. 4, pp. 707-713, Aug. 1997.
[16] S. H. Bang, B. J. Sheu, T. H. Wu, "Optimal solutions for cellular neural networks by paralleled hardware annealing," IEEE Trans. on Neural Networks, vol. 7, no. 2, pp. 440-454, Mar. 1996.
[17] R. C. Chang, B. J. Sheu, J. Choi, D. C. Chen, "Programmable-weight building blocks for analog VLSI neural network processors," Jour. of Analog ICs and Signal Processing, Kluwer Academic Publishers, vol. 9, pp. 215-230, Apr. 1996.
[18] T. Wu, B. J. Sheu, E. Y. Chou, "Behavioral simulation of densely-connected analog cellular array processors for high-performance computing," Jour. of Analog ICs and Signal Processing, Kluwer Academic Publishers, vol. 10, pp. 77-88, June 1996.
[19] S. H. Bang, B. J. Sheu, E. Y. Chou, "A hardware annealing method for optimal solutions on cellular neural networks," IEEE Trans. on Circuits and Systems II, vol. 43, no. 6, pp. 409-421, June 1996.
[20] S. H. Bang, B. J. Sheu, "A neural network for detection of signals in communication," IEEE Trans. on Circuits and Systems I, vol. 43, no. 8, pp. 644-655, Aug. 1996.
[21] S. H. Bang, O. T.-C. Chen, J. C.-F. Chang, B. J. Sheu, "Paralleled hardware annealing in multi-level Hopfield neural networks for optimal solutions," IEEE Trans. on Circuits and Systems II, vol. 42, no. 1, pp. 46-49, Jan. 1995.
[22] S. H. Bang, J. Choi, B. J. Sheu, R. C. Chang, "A compact low-power VLSI transceiver for wireless communication," IEEE Trans. on Circuits and Systems, Part I, vol. 42, no., 11, pp. 933-945, Nov. 1995.
Conference
[1] T. W. Berger, J. L. Granacki, V. Z. Marmarelis, B. J. Sheu, A. R. Tanguay Jr., “Brain-Implantable Biomimetic Electronics and Neural Prosthetics,” Proceedings of 1st International IEEE EMBS Conference on Neural Engineering, pp. 108-111, Capri Island, Italy Mar. 2003.
[2] Y. Park, S. H. Jen, B. J. Sheu, H. Yoon, I. G. Kim, “An Efficient Parameter Extraction Method Using Statistical Optimization in S-CMOS Deep-Submicron/Nanometer Model,” IEEE Symposium on Circuits and Systems, V:233-236, Phoenix, AZ, May 2002.
[3] Y. D. Lee, B. J. Sheu, W. Young, "Intelligent data acquisition and processing for managing higher-education priorities in modern era," IEEE Int’l Symposium on Circuits and Systems, Monterey, CA, May 1998.
[4] R. H. Tsai, B. J. Sheu, M. Y. Wang, S. Jen, "Two-dimensional cellular neural networks for pre-processing in face recognition and digital library search," IEEE Int'l Symposium on Circuits and Systems, pp. 733-736, Hong Kong, June 1997.
[5] D. C. Chen, B. J. Sheu, W.-C. Fang, "A neural network based CDMA detector with robust near-far resistance," IEEE Int'l Symposium on Circuits and Systems, pp. 2120-2123, Hong Kong, June 1997.
[6] W. Young, B. J. Sheu, A. Chu, "Toward computing at the atomic scale," IEEE International Conference on Next Decades of High Technologies, Taiwan, July 1997.
[7] K. B. Cho, B. J. Sheu, "Toward powerful intelligent machines," IEEE International Conference on Next Decades of High Technologies, Taiwan, July 1997.
[8] W.-C. Fang, G. Yang, B. Pain, B. J. Sheu, "A low power smart vision system based on active pixel sensor integrated with programmable neural processor," IEEE International Conference on Computer Design, pp. 429-434, Austin, TX, Oct. 1997.
[9] W.-C. Fang, B. J. Sheu, J. Wall, "On-board neural processor design for an intelligent multi-sensor microspacecraft," SPIE Conference on Applications and Science of Artificial Neural Networks II, vol. 2760, pp. 577-588, Orlando, FL, Apr. 1996.
[10] B. J. Sheu, D. C. Chen, "1-D compact neural networks for wireless communication and mobile computing," IEEE International Symposium on Circuits and Systems, Atlanta, GA, vol. 3, pp. 551-554, May 1996.
[11] S. H. Jen, Y. Oshima, B. J. Sheu, "An improved method for MOS transistor output conductance," IEEE International Symposium on Circuits and Systems, Atlanta, GA, vol. 4, pp. 448-451, May 1996.
[12] R. H. Tsai, T. W. Berger, B. J. Sheu, "VLSI design for real-time signal processing based on biologically realistic neural models," IEEE International Conference on Neural Networks, Washington, DC, pp. 676-681, June 1996.
[13] D. C. Chen, B. J. Sheu, E. Y. Chou, "A neural network communication equalizer with optimized solution capability," IEEE International Conference on Neural Networks, Washington, DC, 1957-1962, June 1996.
[14] D. C. Chen, B. J. Sheu, "A compact neural network based CDMA receiver for multimedia wireless communication," IEEE International Conference on Computer Design, pp. 99-103, Austin, TX, Oct. 1996.
[15] B. J. Sheu, "Constructing intelligent microsystems with modular VLSI neural networks design," IEEE Int'l Symposium on Circuits and Systems, pp. 2100-2103, Seattle, WA, May 1995.
[16] B. J. Sheu, "Constructing intelligent microsystems with modular VLSI neural networks design," IEEE Int'l Symposium on Circuits and Systems, pp. 2100-2103, Seattle, WA, May 1995.
[17] R. C. Chang, B. J. Sheu, S. H. Bang, "Current-mode implementation of CNNs with annealing capability," INNS/World Conress on Neural Networks, vol. II, pp. 488-491, Washington, DC, July 1995.
[18] B. J. Sheu, S. H. Bang, R. C. Chang, "A cellular neural network with optimized performance for wireless communication receivers," INNS/World Congress on Neural Networks, vol. II, pp. 660-664, Washington, DC, July 1995.
[19] E. Y. Chou, B. J. Sheu, T. H. Wu, R. C. Chang, "VLSI design of densely-connected array processors," IEEE International Conference on Computer Design, pp. 492-497, Austin, Texas, Oct. 1995.
[20] W.-C. Fang, B. J. Sheu, H. Venus, R. Sandau, "Smart-pixel array processors and optimal cellular neural networks for space sensor applications," IEEE International Conference on Computer Design, pp. 703-708, Austin, Texas, Oct. 1995.
[21] T. W. Berger, B. J. Sheu, R. Tsai, M. Saglam, "Analog VLSI implementation of a nonlinear model of hippocampus," Society for Neuroscience Abstracts, vol. 21, 1995.
[22] T. W. Berger, B. J. Sheu, V. Z. Marmarelis, R. J. Sclabassi, "A nonlinear system analytic approach to modeling biological neural networks," Abstracts of the Biomedical Engineering Society Meeting, 1995.
[23] B. J. Sheu, R. H. Tsai, E. Y. Chou, T. Berger, "A hippocampal model implementation using VLSI table-llok-up and model-based approaches," IEEE Int'l Conference on Neural Networks, vol. 2, pp. 1508-1512, Perth, Australia, Nov. 1995.
[24] E. Y. Chou, B. J. Sheu, "A compact VLSI design for cellular neural network with hardware annealing capability," IEEE Int'l Conference on Neural Networks, vol. 3, pp. 1650-1655, Perth, Australia, Nov. 1995.
Patent
[1] B. J. Sheu, et al, Wide-range Quick Tunable Transistor Model, TSMC, filed Dec. 2009.
[2] B. J. Sheu, et al, US Patent filling no 200910146984.3, Generating Models for Integrated Circuits with Sensitivity-Based Minimum Change to Existing Models, TSMC, filed 2008.
[3] B. J. Sheu, S. H. Bang, T. W. Berger, One-Dimensional Signal Processor With Optimized Solution Capability, U. S. Patent Number 5,764,858, Date Of Patent: June 9, 1998.
[4] W.-C. Fang, B. J. Sheu, Data Compression Neural Network with Winner-Take-All Function, U.S. Patent Number 5,812,700, Date of Patent: Sept. 22, 1998.
[5] W.-C. Fang, B. J. Sheu, Motion Video Compression System with Neural Network Having Winner-Take-All Function, U.S. Patent Number 5,598,354, Date of Patent: June 9, 1997.
Book
[1] Bing Sheu, “21th Century Youth to Foresee the Future, Embrace the Future, Win the Future” (21世紀年輕人看清未來、擁抱未來、戰勝未來)” NTU EE Alumni Newsletters, vol. 36, 37, 38 (Part 1, Part 2, & Part 3), May/August/December 2010.
[2] Bing Sheu, L.-G. Chen, W.-Z. Chen, C. Y. Wu, “Sharing 2009 Experiences on Innovative Mentoring in SoC field in Taiwan,” IEEE Circuits and Systems Society e-Newsletters, vol. 3, no. 5, Oct. 2009.
[3] Bing Sheu, Pei-Hua Chen, “Revealing IEEE Fellows Unknown” (掀開『國際電機電子學會』會士的神秘面紗,) NTU EE Alumni Newsletters, vol. 32 & 33 (Part 1 & Part 2), 2009
[4] Bing Sheu, Morris Ker, Chin-Teng Lin, Peter Wu, "Sharing 2007/2008 Globalization Leadership Mentoring Experiences in Taiwan," IEEE Circuits and Systems Society e-Newsletters, vol. 2, no. 2, April 16, 2008.
[5] B. J. Sheu, “Searching for Golden Key of Engineering Academia (環環相扣、工程學術的金鑰匙在哪裡?)” vol. 52, National Taiwan University Alumni Newsletters, July 2007. e論壇2 http://www.alum.ntu.edu.tw/read.php?num=52&sn=1260&check
[6] B. J. Sheu, “Facing Challenges to the Youth in 21st Century (勇敢面對21世紀年輕人的新挑戰,)” NTU EE Alumni Newsletters, vol. 24 & 25, (Part 1) May 2007 & (Part 2) Aug. 2007.
[7] Bing Sheu, Ming-Dou Ker, "Sharing Globalization Leadership Mentoring Program Experience at Selective Universities in Taiwan," IEEE Circuits and Systems Society e-Newsletters, vol. 1, no. 2, April 16, 2007.
[8] B. J. Sheu, C. Y. Wu, M.-D. Ker, Pursuit of 21st Century Golden Key: Nurturing Young Generation to Grasp Opportunities (in Chinese and 1-chapter in English), ISBN 978-98682-99740, Sept. 2007.
[9] C.Y. Wu, B. J. Sheu, 21st Century Modern Education Insights (in Chinese), National Chiao Tung University Press, ISBN 986-81857-5-0, Apr. 2006.
[10] T. W. berger, R. D. brinton, V. Z. marmarelis, B. J. Sheu, A. R. Tanguay, Brain-Implantable Biomimetic Electronics as a Neural Prosthesis for Hippocampal Memory Function, Chapter 12 in Toward Replacement Parts for the Brain, Eds. T. W. berger, D. L. Glanzman, (ISBN 0-262-02577-9), MIT Press, 2005.
[11] R. C. Chang, B. J. Sheu, Transmission Gates, Chapter 12.4.2 in Circuits and Filters Handbook, W.-K. Chen, Ed., CRC Press & IEEE Press, 1995, & 2nd Edition, 2003.
[12] J. C. Chang, B. J. Sheu, MOS Storage Circuits, Chapter 12.5.4 in Circuits and Filters Handbook, W.-K. Chen, Ed., CRC Press & IEEE Press, 1995; & 2nd Edition, 2003
Other
[1] B. J. Sheu, “Vivid New Thinking and New Approaches in 21st Century,” pp. 1-3 to 1-13, Book: 21st Century Modern Education Insights, NCTU Press, ISBN 986-81857-5-0, Apr. 2006.
[2] X. Du, B. J. Sheu, “Modeling Ferroelectric Capacitors for Memory Applications,” IEEE Circuits and Devices Magazine, vol. 17, no.6, Nov. 2002.
[3] E. Y. Chou, B. J. Sheu, “Nanometer Mixed-signal System-on-a-Chip Design,” IEEE Circuits and Devices Magazine, vol. 18, no. 4, pp. 7-17, July. 2002.
[4] E. Y. Chou, B. J. Sheu, “System-on-a-Chip Design for Modern Communications,” IEEE Circuits and Devices Magazine, vol. 17, no. 6, pp. 12- 17, Nov. 2001.
[5] C.-H. Cheng, C.-Y. Wu, B. J. Sheu, et al., “In the Blink of a Silicon Eye,” IEEE Circuits and Devices Magazine, vol. 17, no. 3, pp. 20-32, May 2001.
[6] B. Aghdaie, B. J. Sheu, “Lumped MOS models, transient fast signal handling in RF applications,” IEEE Circuits and Devices Magazine, vol. 16, no. 2, pp. 19- 26, Mar. 2000.

Project
Title Total Amount Excution Duration Client
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Student
Ph.D
M.S
Student's Project
Student's Honor