Faculty

photo
Shanq-Jang Ruan　Associate Professor
Position
Associate Professor
Education
Ph.D., National Taiwan University　
E-mail
sjruan@mail.ntust.edu.tw
Room
IB 714-2
Telephone
886-2-2737-6411
FAX
886-2-27376424
Homepage
Laboratory
Major Field
Hardware/Software analysis and optimization for embedded systems, Electronic Design Automation, High performance and low power design.
Course
Computer architecture, computer organization, Discrete Math., low power SoC design

Record
2007.08
~
 迄今 Associate Professor at Dept. of Electronic Engineering of NTUST
2003.08
~
 2007.07 Assistant Professor at Dept. of Electronic Engineering of NTUST
2002.06
~
 2003.07 Senior Software Engineer, Synopsys
2001.09
~
 2002.05 Software Engineer, Avant!

Research

Honor & Awards
2009
 2009 IC Design Contest, FPGA design, Excellent Award
2009
 獲98年度教育部學海築夢計畫獎助案，前往紐西蘭Unitec科技電院電子科技學系進行參訪
2008
 IICM Master Thesis Award (Master Student Yi-Fan Chang)資訊學會最佳碩博士論文獎
2006
 IICM Master Thesis Award (Master Student Chi-Chia Sun)資訊學會最佳碩博士論文獎
2005
 IICM Master Thesis Award (Master Student 許正良)資訊學會最佳碩博士論文獎
2005
 IICM Master Thesis Award (Master Student 林柏耀)資訊學會最佳碩博士論文獎

Research (2000~)
Journal
  • Shanq-Jang Ruan,Jui-Yuan Hsieh, and Chia-Han Lee, "Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory," IEICE Transactions on Electronics (special issue on Hardware and Software Technologies on Advanced Microprocessors), Vol.E92-C,No.10,pp.-,Oct. 2009. (SCI/EI)
  • Yu-Ting Pai, Li-Te Lee, Shanq-Jang Ruan, Yen-Hsiang Chen, Saraju Mohanty, Elias Kougianos, "Honeycomb Model Based Skin Color Detector for Face Detection" International Journal of Computer Applications in Technology (IJCAT), 2009 (accept)
  • Shanq-Jang Ruan and Shang-Fang Tsai, "DS2IS: Dictionary-based Segmented Inversion Scheme for Low Power Dynamic Bus Design," Journal of Systems Architecture, Vol. 54, Issue 1-2, pp. 324-334, 2008. (SCI)
  • Shanq-Jang Ruan, Chi-Yu Wu, and Jui-Yuan Hsieh, "Low Power Design of Precomputation-based Content Addressable Memory," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 3, pp. 331-335, Mar. 2008. (SCI/EI)
  • Chi-Chia Sun, Sanq-Jang Ruan, B. Heyne and J. Goetze, "Low-power and High-quality Cordic-based Loeffler DCT for Signal Processing," IET (IEE) Circuit Devices & System, vol.1, pp. 453-461, Dec. 2007. (SCI/EI)
  • Yu-Ting Pai and Shanq-Jang Ruan, "A High Quality Robust Digital Watermarking by Smart Distribution Technique and Effective Embedded Scheme," IEICE Transaction on Fundamentals, Vol. E90-A, No. 3, pp. 597-605, March, 2007. (SCI/EI)
  • Yu-Ting Pai and Shanq-Jang Ruan, "Low Power Block-based Watermarking Algorithm," IEICE Transaction on Information and Systems, Vol. E89-D, No. 4, pp. 1507-1514, April 2006. (SCI/EI)
  • Edwin Naroska, Shanq-Jang Ruan and Uwe Schwiegelshohn, "Simultaneously Optimizing Crosstalk and power for Instruction Bus Coupling Capacitance Using Wire Pairing," IEEE Transactions on Very Large Scale Integration System, Vol. 14, No. 4, pp. 421-425, Apr. 2006. (SCI/EI) (NSC 93-2213-E-011-062-)
  • Chi-Chia Sun, Shanq-Jang Ruan, Mon-Chau Shie and Tun-Wen Pai, "Dynamic Contrast Enhancement based on Histogram Specification," IEEE Transactions on Consumer Electronics, Vol. 51, Issue 4, Nov. 2005, pp. 1300-1305. (SCI/EI)
  • Chi-Chia Sung, Shanq-Jang Ruan, Bo-Yao Lin, and Mon-Chau Shie, "Quality and Power Effcient Architecture for the DiscreteCosine Transform," IEICE Transactions on Fundamentals, Vol. E88-A, No. 12, pp. 3500-3507, Dec. 2005. (SCI/EI)
  • Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska and Feipei Lai, "Bipartitioning and Encoding in Low Power Pipelined Circuits," ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No.1, pp. 24-32, Jan. 2005. (NSC 92-2218-E-011 -006) (SCI)
  • Kun-Lin Tsia, Shanq-Jang Ruan, Chun-Ming Huang, Edwin Naroska, and Feipei Lai "Circuit Partition and Reordering Technique for Low Power IP Design" IEICE Transactions on Electronics, Vol. E87-C, No. 4, pp. 613-620, Apr. 2004 (SCI/EI)
  • Yen-Jen Chang, Shanq-Jang Ruan, and Feipei Lai, "Design and Analysis of Low Power Cache using Two-Level Filter Scheme", IEEE Transactions on Very Large Scale Integration Systems. Vol. 11, No. 4, pp. 568-580, Aug. 2003 (SCI/EI)
  • Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn, "ENPCO: An Entropy-Based Partition-Codec Algorithm to ReducePower for bipartition-codec architecture in Pipelined Circuits," IEEE Transactions on Very Large Scale Integration Systems, Volume 10, Issue 6, Dec. 2002, pp. 942-949. (SCI/EI)
  • Kuen-PinWu, Shanq-Jang Ruan, Chih-Kuang Tseng, and Feipei Lai, "Hierarchical Access Control Using the Secure Filter", IEICE Transactions on Information and Systems. Vol. E84-D, No. 6, pp. 700-708, June 2001. (SCI/EI)
  • Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin. Tsai, "A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits, "IEEE Transactions on Computer Aided Design of Integrated Circuits. Vol. 20, No. 2, pp. 343-348, Feb. 2001. (SCI/EI)
Conference
  • Fan-Chieh Cheng, Shih-Chia Huang, and Shanq-Jang Ruan, "Advanced Motion Detection for Intelligent Video Surveillance Systems" 25th ACM Symposium on Applied Computing, Lausanne, Switzerland, Mar. 22-26, 2010. (Accepted)
  • Yu-Ting Pai, Chia-Han Lee, and Shanq-Jang Ruan, "An Improved Comparison Circuit for Low Power Pre-Computation-Based Comtent-Addressable Memory Design," IEEE International Conference on Electronics, Circuits and Systems (ICECS 2009), Tunisia, 13th Dec. - 16th Dec. 2009. (accepted)
  • Li-Te Lee, Yu-Ting Pai, Shanq-Jang Ruan,and Jürgen Götze, "An Energy Efficient and High Security Watermarking Mechanism Based on DS-CDMA," in proceeding of 2009 IEEE International Conference on Multimedia & Expo (ICME 2009), New York, USA, June 28 - July 3, 2009, pp. 1190-1193
  • Chia-Shaud Hung, Yen-Hsiang Chen, Yi-Fan Chang, and Shanq-Jang Ruan, "An Efficient Thresholding Algorithm for License Palte Recognition Based on Intelligent Block Detection," The 4th Conference on Industrial Electronics and Application (ICIEA 2009), Xi'an, China, 25-27 May, 2009, pp 236-240
  • Kai-Ti Hu, Yu-Ting Pai, and Shanq-Jang Ruan, "Exploring the tradeoff between Power and Detection Rate for a Face Detection Algorithm," The 4th Conference on Industrial Electronics and Application (ICIEA 2009), Xi'an, China, 25-27 May, 2009, pp. 3619-3622
  • Yu-Ting Pai, Li-Te Lee, Shanq-Jang Ruan, Yen-Hsiang Chen, Saraju Mohanty, Elias Kougianos, "Honeycomb Model Based Skin Color Detector for Face Detection" 15th International Conference on Mechatronics and Machine Vision in Practice on 2 - 4 December 2008 pp.11-16
  • Chen, Yen-Hsiang; Chen, Shu-Song; Ruan, Shanq-Jang, "Integrating Bi-Direction Audio and Video Transmission for UltraVNC" Fourth International Conference on Networked Computing and Advanced Information Management (NCM2008), Volume 2, 2-4 Sept. 2008 Page(s): 505 - 508
  • Kun-Lin Tsai, Paul Lan, Shanq-Jang Ruan, and Mou-Chau Shie, "A low power high performance design for JPEG Huffman decoder," The 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, 31st Aug. - 3rd Sep. 2008, pp.1151-1154
  • Kashif Samee, M.Gotze.J,Shanq-Jang Ruan, Yu-Ting Pai, "Digital watermarking: Spreading code versus channel coding" 3rd International Symposium on Communications, Control and Signal Processing(ISCCSP), 12-14 March 2008 Page(s): 1409 - 1412
  • Shanq-Jang Ruan, Kun-Lin Tsai, Wen-Yew Liang, "A study on battery life tradeoff between deep sleep and sleep modes of an actual PDA" The 3rd IEEE Conference on Industrial Electronics and Applications (ICIEA 2008), 3-5 June 2008 Page(s): 2019 - 2024
  • Wen-Yew Liang, Yang-Lang Chang, Jyh-Perng Fang, Shanq-Jang Ruan, Hung-Che Lee, Chi-Yu Weng, "Supporting dynamic distributed computing for industrial devices and applications" The 3rd IEEE Conference on Industrial Electronics and Applications (ICIEA 2008), 3-5 June 2008 Page(s): 2013 - 2018
  • Muhammad Kashif Samee, Jurgen Gotze, Shanq-Jang Ruan and Yu-Ting Pai, "Digital watermarking: Spreading code versus channel coding ," 3rd International Symposium on Communications, Control and Signal Processing(ISCCSP), pp. 1409-1412, Malta, 12nd-14th March 2008.
  • Yi-Fan Chang, Yu-Ting Pai, and Shanq-Jang Ruan, "An Efficient Thresholding Algorithm for Degraded Document Images based on Intelligent Block Detection," 2008 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2008), Singapore, 12 - 15 October 2008. (EI)(accepted)
  • Jui-Yuan Hsieh and Shanq-Jang Ruan, "Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory Using Gate-Block Selection Algorithm," ACM/IEEE 2008 Asia and South Pacific Design Automation Conference (ASP-DAC), Korea, 21st -24th January, 2008, pp. 316-321
  • Shanq-Jang Ruan and Wei-Te Lin, "Bipartition Architecture for Low Power JPEG Huffman Decoder," The 12th Asia-Pacific Computer Systems Architecture Conference, Korea, 23rd-25th, August , 2007, pp. 235-243
  • Shanq-Jang Ruan and Shang-Fang Tsai, "Design and Analysis of Low Power Dynamic Bus Based on RLC Simulation," IEEE Computer Society Annual Symposium on VLSI 2007, Brazil, 9th-11th, May, 2007, pp. 113 - 118
  • Yen-Jen Chang, Yuan-Hong Liao and Shanq-Jang Ruan, "Improve CAM Power Efficiency Using Decoupled Match Line Scheme," ACM DATE 2007, Nice France, Apri. 16-20, pp.165-170
  • Chin-Kun Wen, Yi -Ruei Lai, and Shanq-Jang Ruan, "Design and Implementation of 2.4GHz Wireless Skype Phone," 2006 International Computer Symposium, Taipei, Taiwan, December 4, 2006, pp. 45-49
  • Shanq-Jang Ruan and Yi -Ruei Lai, "Development and Analysis of Power Behavior for Embedded System Laboratory", ACM Workshop on Embedded System Education, October 26, 2006 Seoul, South Korea, pp.45-50
  • Shang-Fang Tsai and Shanq-Jang Ruan, “DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design,” in proceeding of 9th International Conference on Information Technology (ICIT2006), Bhubaneswar, India, 18th-21st December 2006, pp. 293-296.
  • Yu-Ting Pai, Shanq-Jang Ruan, and Jürgen Götze, “A High Quality Robust Watermarking Scheme,” in proceeding of Pacific-Rim Conference on Multimedia 2006 (PCM 2006), China, , Vol. 4261(LNCS), pp. 650-657, Nov. 2nd-4th, 2006. (SCIE) (accept rate: 15%)
  • Chiu-Yi Chen, Yu-Ting Pai, and Shanq-Jang Ruan, "Low Power Huffman Coding for High Performance Data Transmission," in proceeding of IEEE The First International Conference on Hybrid Information Technology, Cheju Island, Korea, Nov. 9-11, 2006. pp. 71-77 (accept rate: 25%)
  • Benjamin Heyne, Chi-Chia Sun, Juergen Goetze, and Shanq-Jang Ruan, "A Computationally Efficient High-Quality Cordic Based Loeffler DCT," in proceeding of 2006 14th European Signal Processing Conference, Florence, Italy, Sep. 4-8, 2006.
  • Yu-Ting Pai, Shanq-Jang Ruan, Mon-Chau Shie, and Yi-Chi Liu, "A Simple and Accurate Color Face Detection Algorithm in Complex Background," in proceeding of 2006 IEEE International Conference on Multimedia & Expo (ICME 2006), Canada, 9-12 July 2006, pp. 1545-1548. (EI)
  • Jyun-Yuan Cheng, Shanq-Jang Ruan, Ray-Guang Cheng, and Teng-Tai Hsu, "PADCP: Power-Aware Dynamic Clustering Protocol for Wireless Sensor network", in proceeding of 3rd IFIP and IEEE International Conference on Wireless and Optical Communications Networks (WOCN 2006), India, 11-13 April 2006.
  • Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, and Fiepei Lai, "Low Power Scheduling Method using Multiple Supply Voltages," in proceeding of IEEE International Symposium on Circuits and Systems, May 2006. (EI)
  • Yi-Ruei Lai and Shanq-Jang Ruan, "Power Analysis of Computer Game Algorithms for Handheld Embedded System," in proceeding of 1st IEEE International Conference on Industrial Electronics and Applications (ICIEA 2006), Singapore May 24-26 2006. (EI)
  • Li-Wei Cheng and Shanq-Jang Ruan, "Automated Measurement System for Quality Control of AMLCD Manufacturing," in proceeding of 1st IEEE International Conference on Industrial Electronics and Applications (ICIEA 2006), Singapore May 24-26 2006. (EI)
  • Chi-Chia Sun, Benjamin Heyne, Shanq-Jang Ruan and Juergen Goetze, "A Low-Power and High-Quality Cordic Based Loeffler DCT," in proceeding of 2006 International Symposium on VLSI Design, Automation & Test (VLSI-DAT 2006), Hsinchu, Taiwan April 26-28, 2006, pp. 102-105.
  • Shanq-Jang Ruan, Edwin Naroska, and Chun-Chih Chen, “Optimal Partitioned Fault-Tolerant Bus Layout for Reducing power in Nanometer Designs”, in Proceedings of ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, pp. 114-119, April 2006. (EI)
  • Chi-Yu Wu, Shanq-Jang Ruan, Ming-Bo Lin, Chung-Kai Cheng, "A New Block-XOR Precomputation-Based CAM Design For Low-Power Embedded System," 12th IEEE International Conference on Electronics, Circuits and Systems Gammarth, Tunisia, December 11-14th 2005. (EI)
  • Yu-Ting Pai, Shanq-Jang Ruan and Jürgen Götze, "Energy-Efficient Watermark Algorithm Based on Pairing Mechanism," in proceeding of International Workshop on Intelligent Information Hiding and Multimedia Signal Processing, Australia, Vol. 3681, pp. 1219-1225, 14-16 Sept. 2005.(SCI E)
  • Kun-Lin Tsai, Szu-Wei Chang, Feipei Lai, and Shanq-Jang Ruan , "A Low Power Scheduling Method using Dual Vdd and Dual Vth," IEEE International Symposium on Circuits and Systems, 23-26 May 2005 pp. 684 - 687 (EI)
  • Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn, and Feipei Lai, "Optimal Permutation and Spacing for Unbiased-Random, Counter, and Instruction Address Buses," The 3rd International IEEE-NEWCAS Conference, 19-22 June, 2005 pp. 332 - 335 (EI)
  • Kun-Lin Tsai, Shanq-Jang Ruan, Li-Wei Chen, Feipei Lai and Naroska E., "Low Power Dynamic Bus Encoding for Deep Sub-micron Design," The 3rd International IEEE-NEWCAS Conference, 19-22 June, 2005 pp. 170 - 173
  • Bo-Yao Lin, Chi-Chia Sung, Shanq-Jang Ruan, and Mon-Chau Shie "A Novel DCT Architecture for Quality and Power Efficient" IEEE International Workshop on Nonlinear Signal and Image Processing (NSIP 2005), May 2005 pp. 151 - 156
  • Edwin Naroska, Shanq-Jang Ruan, and Uwe Schwiegelshohn "An Efficient Algorithm for Simultaneous Wire Permutation, Inversion, and Spacing," IEEE International Symposium on Circuits and Systems, 23-26 May 2005 pp. 109 - 112 (NSC93-2213-E011-062) (EI)
  • Shanq-Jang Ruan, Edwin Naroska, and Uwe Schwiegelshohn, "Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design" in Proceeding of 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2005), 04-08 April 2005 pp. 233a - 233a (NSC 92-2218-E-011 -006 ) (EI)
  • Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, and Szu-Wei Chaung, "State Reordering for Low Power Combinational Logic," The Eighth Asia-Pacific Computer System Architecture Conference, Sep. 2003 pp. 268-276.
  • Edwin Naroska , Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le Chin Liu, "On Optimizing Power and Crosstalk for Bus Coupling Capacitance using Genetic Algorithms", IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 277 –280, May 25-28, 2003. (EI)
  • Shanq-Jang Ruan, Edwin Naroska, Yen-Ren Chang, Chia-Lin Ho, FeipeiLai, "Energy Analysis of Bipartition Architecture for Pipelined Circuits" in proceeding of IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 2, 28-31, Oct. 2002 pp. 7 - 11. (EI)
  • Yen-Jen Chang, Feipei La, Shanq-Jang Ruan, "Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost", in proceeding of IEEE International Conference on Computer Design, pp. 334 -339, Sept. 2002. (EI)
  • Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai, "Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits" in proceeding of IEEE International Conference on Computer Design, pp. 327-332, Sep. 2002. (EI)
  • Yen-Jen Chang, Feipei Lai and Shanq-Jang Ruan, “An Efficient Two-Level Filter Scheme for Low Power Cache,” IEEE/ACM 11th International Workshop on Logic & Synthesis (IWLS 2002), New Orleans, Louisiana, June 4-7, 2002, pp.61-66.
  • Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hong Chen, Kun-Lin Tsai, Feipei Lai, "Synthesis of Partition-Codec Architecture for Low Power and Small Area Circuit Design," in proceeding of IEEE International Conference on Circuits and Systems, pp. V523-V526, 2001. (EI)
  • Po-Hung Chen, Shanq-Jang Ruan, Kuen-PinWu, Dai-Xun Hu, Feipei Lai,Kun-Lin Tsai, "An Entropy-Based Algorithm to Reduce Area Overhead for Bipartition-Codec Architecture," in proceeding of IEEE International Conference on Circuits and Systems, pp. V49-V52, 2001. (EI)
  • Shanq-Jang Ruan, Jen-Chiun. Lin, Po-Hong Chen, Feipei Lai, Kun-Lin Tsai and Chung-Wei Yu, "An Effective Output-Oriented Algorithm for Low Power Multipartition Architecture," 7th IEEE International Conference on Electronics,Circuit and System, pp. 609-612, Dec. 2000.
  • K.P.Wu, Shanq-Jang Ruan, F. Lai, C.K. Tseng, "On Key Distribution in Secure Multicasting," in Proceedings of 25th IEEE Conference on Local Computer Networks (LCN), pp. 208-212, Nov. 2000. (EI)
Patent
Book
Other

Student
Pd.D
M.S
96
Power Analysis of a Face Detection Program
Jyun-Yuan Wang
96
Synthesis ans Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
Jui-Yuan Hsieh
96
An Efficient Thresholding Algorithm for Degraded Document Image Based on Intelligent Block Detection
Yi-Fan Chang
96
Integrating Bi-Direction Audio and Video Transmission for ultraVNC
Yani-Xiang Chen
95
Design and Anlysis of Low Power Dynamic Bus Based on RLC Simulation
Shang-Fang Tsai
95
Power-aware Synthesis Flow for Network-on-Chip based on Irregular Topologies
Zuo-Yu Huang
95
Novel Algorithm for LCD Color and Gray Level Response Time Adjustment
Jheng-Cian Yang
95
Power evaluation and design of table partition approach for jpeg huffman decoders
Yang-Po Lan
95
Design of a low power huffman decoder for JPEG using lookup table bipartition technique
Wei-De Lin
94
Synthesis of low power PB-CAM
Chun-Chih Chen
94
A New Block-XOR Precomputation-Based Content Addressable Memory for Low Power System
Chi-Yu Wu
94
PADCP: Power-Aware Dynamic Clustering Protocal for Wireless Sensor Network
Jyun-Yuan Cheng
94
Power Analysis of Computer Game Algorithm for Handheld Enbedded System
Yi -Ruei Lai
94
Cordic based Loeffler DCT架構
Chi-Chia Sun
94
The Impact of CPU Deep Sleep Mode on Battery Lifetime of Personal Digital Assistants
Tsung-Yi Liu
93
A Novel DCT Architecture for Quality and Power Efficiency
Po-Yao Lin
93
An Implementation of a Measurement Flow for LCD Displaying Characteristics
Li-Wei Cheng
93
Wire Permutation and Spacing for Low Power Fault-Tolerant Bus
Cheng-Liang Hsu