Faculty

Randall Geiger Randall Geiger photo
Position
Honorary Chair Professor
Education
PhD, Colorado State University
E-mail
rlgeiger@iastate.edu
Room
Room 351 Durham, Dept. ECE, Iowa St

Office Hours
Telephone
FAX
Homepage http://class.ece.iastate.edu/rlgeiger/
Laboratory
Major Field analog and mixed-signal VLSI design, ADC/DAC design and test, IC layout optimization and yield enhancement
Course



2005 IEEE Fellow Committee
2002 Willard and Leitha Richardson Professor
2000 IEEE Millenium Medal
2000 IEEE Circuits and Systems Society Golden Jubilee Medal
1996 Meritorious Service Award, IEEE Circuits and Systems Society
1993 Chairman, IEEE Periodicals Council
1992 President, IEEE Circuits and Systems Society
1990 IEEE Fellow

Research Achievement
  [1]   Le Jin; Haggag, H.; Geiger, R.L.; Degang Chen, “Testing of Precision DAC Using Low-Resolution ADC With Wobbling,” IEEE Trans on Instr. and Measurement, Vol. 57, pp. 940 - 946, May 2008.
  [2]   He, C.; Jin, L.; Chen, D.; Geiger, R.; “Robust High-Gain Amplifier Design Using Dynamical Systems and Bifurcation Theory With Digital Postprocessing Techniques,” IEEE Trans. on Circuits and Systems I, Vol. 54, pp. 964 - 973, May 2007.
  [3]   Hanjun Jiang; Olleta, B.; Degang Chen; Geiger, R.L., “Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs,” IEEE Trans on Instr. and Measurement, Vol. 56, pp. 1753 - 1762, Oct. 2007.
  [4]   Le Jin; Degang Chen; Geiger, R.L., “SEIR Linearity Testing of Precision A/D Converters in Nonstationary Environments With Center-Symmetric Interleaving,” IEEE Trans on Instr. and Measurement, vol. 56, pp. 1776 - 1785, Oct. 2007.
  [5]   Y. Lin, D. Chen and R.L. Geiger “Yield Enhancement With Optimal Area Allocation for Ratio-Critical Analog Circuits”, IEEE Trans. on Circuits and Systems I, Vol 53, pp. 534-553, March 2006.
  [6]   Oletta, B., Jiang, H. Chen, D.J. and Geiger, R.L. “A Deterministic Dynamic Element Matching Approach for Testing High Resolution ADCs with Low Accuracy Excitations”, IEEE Trans on Instr. and Measurement, Vol. 55, pp. 902 – 915, June 2006.
  [1]   Hanqing Xing, Degang Chen, Geiger R., Le Jin,"System identification -based reduced-code testing for pipeline ADCs’linearity test", IEEE International Symposium on Circuits and Systems,pp.2402-2405 ,May 2008
  [2]   Hanqing Xing, Degang Chen, Geiger R.,"On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering"",IEEE International Conference on Electro/Information Technology,PP. 117-122,May 2008
  [3]   Sloat J.D., Geiger R.L.,"An inexpensive microelectronic environmental test chamber",IEEE International Conference on Electro/Information Technology,PP. 168-170,May 2008
  [4]   Jun He, Sanyi Zhan, Degang Chen, Geiger R.,"A simple and accurate method to predict offset voltage in dynamic comparators",IEEE International Symposium on Circuits and Systems, pp. 1934-1937, May 2008
  [5]   Katyal V., Geiger R.L., Chen D.J.,"Adjustable hysteresis CMOS Schmitt triggers",IEEE International Symposium on Circuits and Systems, pp. 1938-1941, May 2008
  [6]   Jun He, Geiger. R, Degang Chen,"A detailed analysis of nonideal effects on high precision bandgap voltage references",Midwest Symposium on Circuits and Systems,pp382-385,Aug. 2008
  [7]   Yingkun Gai, Geiger. R, Degang Chen,"Noise analysis in hold phase for switched-capacitor circuits",Midwest Symposium on Circuits and Systems,pp.45-48,Aug. 2008
  [8]   Le Jin, Degang Chen, Geiger R.,"Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal", IEEE VLSI Test Symposium,pp.303-310,May 2007
  [9]   Hanjun Jiang, Degang Chen, Geiger R.L.,"Deterministic DEM DAC Performance Analysis", IEEE International Symposium on Circuits and Systems,pp.3860-3863,May 2007
  [10]   Hanqing Xing, Hanjun Jiang, Degang Chen, Geiger R.,"A fully digital-compatible BIST strategy for ADC linearity testing",IEEE International Test Conference,pp. 1-10,Oct. 2007
  [11]   Hanqing Xing, Le Jin, Degang Chen, Geiger. R, " Characterization of a current-mode bandgap circuit structure for high-precision reference applications", IEEE International Symposium on Circuits and Systems, pp. 4, May 2006
  [12]   Le Jin, Hanqing Xing, Degang Chen, Geiger. R,"A self-calibrated bandgap voltage reference with 0.5 ppm/°C temperature coefficient", IEEE International Symposium on Circuits and Systems, pp. 4, May 2006
  [13]   Chao Su, Geiger R.L.,"Dynamic calibration of current-steering DAC",IEEE International Symposium on Circuits and Systems,pp.4,May 2006
  [14]   Wada K., Geiger R.L.,"Minimization of total area in integrated active RC filters",IEEE International Symposium on Circuits and Systems,pp.4,May 2006
  [15]   Xin Dai, Degang Chen, Geiger R.,"Explicit characterization of bandgap references",IEEE International Symposium on Circuits and Systems,pp.4,May 2006
  [16]   Yu Lin, Geiger R.,"Unit resistor characterization for matching-critical circuit design",IEEE International Symposium on Circuits and Systems,pp.4,May 2006
  [17]   Fei Haibo, Geiger Randall L.,"Aggressive Area Scaling in Passive Transresistance Networks",IEEE International Midwest Symposium on Circuits and Systems,pp.536 - 539,Aug. 2006
  [18]   Fei Haibo, Geiger Randall L.,"Aggressive Area Scaling in Passive Transresistance Networks", IEEE International Midwest Symposium on Circuits and Systems,pp.536-539,Aug. 2006
  [19]   Le Jin, Degang Chen, Randall Geiger,"Linearity Test of Analog-to-Digital Converters Using Kalman Filtering",IEEE International Test Conference,pp.1 - 9,Oct. 2006
  [20]   Le Jin, Hosam Haggag, Geiger R., Degang Chen,"Testing of Precision DACs Using Low-Resolution ADCs with Dithering",IEEE International Test Conference,pp.1 - 10,Oct. 2006
  [21]   Katyal Vipul, Geiger Randall L., Chen Degang J.,"A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs",IEEE Asia Pacific Conference on Circuits and Systems,pp.5 - 8,Dec. 2006
  [22]   S. Thoka and R.L. Geiger, “Fast-Switching Adaptive Bandwidth Frequency Synthesizer using a Loop Filter with Switched Zero-Resistor Array”, IEEE International Symposium on Circuits and Systems, pp. 5373-5376, Kobe Japan, May 2005.
  [23]   H. Xing, D. Chen, and R.L. Geiger, ”A Two-Step DDEM ADC for Accurate and Cost Effective DAC Testing”, IEEE International Symposium on Circuits and Systems, pp. 4289-4292, Kobe Japan, May 2005.
  [24]   Z. Yu, D. Chen, R.L. Geiger, and Y. Papantonopoulo, “Pipelined ADC Linearity Testing with Dramatically Reduced Capture Time ”, IEEE International Symposium on Circuits and Systems, pp. 792-795, Kobe Japan, May 2005.
  [25]   D. Chen, Z. Yu, and R.L. Geiger, “An Adaptive Truly Background Calibration Method for High Speed Pipeline ADC Design”, IEEE International Symposium on Circuits and Systems, pp. 6190-6193, Kobe Japan, May 2005.
  [26]   W. Liu, H. Xing, L. Jin, R.L. Geiger, and D. Chen, “ A Test Strategy for Time-to-Digital Converters Using Dynamic Element Matching and Dithering”, pp. 3809-3812, IEEE International Symposium on Circuits and Systems, Kobe Japan, May 2005.
  [27]   H. Jiang, B. Olleta, D. Chen, and R.L. Geiger, “ A Segmented Thermometer Coded DAC with Deterministic Dynamic Element Matching for High Resolution ADC Test”, IEEE International Symposium on Circuits and Systems, pp. 784-7887, Kobe Japan, May 2005.
  [28]   L. Jin, D. Chen, and R.L. Geiger, “ A Digital Self-Calibration Algorithm for ADCs Based on Histogram Test Using Low-Linearity Input Signals”, IEEE International Symposium on Circuits and Systems, pp. 1378-1381, Kobe Japan, May 2005.
  [29]   H. Jiang, D. Chen, and R.L. Geiger, “ Dither Incorporated Deterministic Dynamic Element Matching for High Resolution ADC Test Using Extremely Low Resolution DACs, ” IEEE International Symposium on Circuits and Systems, pp. 4285-4288, Kobe Japan, May 2005.
  [30]   X. Dai, C. He, H. Xing, D. Chen, and R.L. Geiger, “ An n-th Order Central Symmetrical Layout Pattern for Nonlinear Gradient Cancellation”, IEEE International Symposium on Circuits and Systems, pp. 4835-4838. Kobe Japan, May 2005.
  [31]   X. Dai, D. Chen, and R.L. Geiger, “ A Cost-Effective Histogram Test-Based Algorithm for Digital Calibration of High-Precision Pipelined ADCs”, IEEE International Symposium on Circuits and Systems, pp. 4831- 4834, Kobe Japan, May 2005.
  [32]   Y. Lin, V. Katyal, M. Schlarmann, and R.L. Geiger, “ kT/C Constrained Optimization of Power in Pipelined ADCs”, IEEE International Symposium on Circuits and Systems, pp. 1968-1971, Kobe Japan, May 2005.
  [33]   V. Katyal, Y. Lin, and R.L. Geiger, “Power Dependence of Feedback Amplifiers on Op Amp Architecture”, IEEE International Symposium on Circuits and Systems, pp. 1618-1621, Kobe Japan, May 2005.
  [34]   Chao Su, Xin Dai and Geiger, R.L., “A novel dynamic calibration approach for current-steering DACS”, Proceedings of the IEEE International Workshop on VLSI Design and Video Technology, pp. 40- 43, Shanghai, May 2005.
  [35]   Parthasarathy, K.m Kuyel, T., Zhongjun Yu, Degang Chen and Geiger, R.L., ”A 16-bit resistor string dac with full-calibration at final test”, IEEE International Test Conference, pp. 66 –75, Nov 2005.
  [36]   Le Jin, Parthasarathy, K., Kuyel, T., Geiger, R and Degang Chen; “High-performance adc linearity test using low-precision signals in non-stationary environments”, IEEE International Test Conference, pp. 1182 – 1191, Nov 2005.
  [37]   Soufi, B.; Malik, S.Q.; Geiger, R.L “A capacitor sharing technique for RSD cyclic ADC”, IEEE Midwest Symposium on Circuits and Systems, pp. 859-862, Cincinnati, Ohio August 2005.
  [38]   Katyal, V., Yu Lin, Geiger, R.L. and Chen, D.J., “Statistical modeling of over-range protection requirement for a switched capacitor inter-stage gain amplifier”, IEEE Midwest Symposium on Circuits and Systems, pp. 1819-1822, Cincinnati, Ohio August 2005.
  [39]   Malik, S.Q.and Geiger, R.L., “Simultaneous capacitor sharing and scaling for reduced power in pipeline ADCs”, IEEE Midwest Symposium on Circuits and Systems, pp. 1015-1018, Cincinnati, Ohio August 2005.
  [40]   Amourah, M.M.; Malik, S.Q.; Geiger, R.L.; “A new design technique for rail-to-rail amplifiers”, IEEE Midwest Symposium on Circuits and Systems, pp. 263-266, Cincinnati, Ohio August 2005.
  [41]   Yu Lin, Katyal, V and Geiger, R.L., “New over-range protection scheme in pipelined data converters” IEEE Midwest Symposium on Circuits and Systems, pp. 283-286, Cincinnati, Ohio August 2005.

Research Achievement
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Student
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