Faculty

Miin-Horng Juang Distinguished Professor
photo
Position
Distinguished Professor
Education
EE Ph.D., National Chiao-Tung University 
E-mail
AK80492@mail.ntust.edu.tw
Room
EE 705-1
Office hour
Mon. 12:00~13:30 Thr. 12:00~13:30
Telephone
886-2-27376436
FAX
Homepage
N/A
Laboratory
Major Field
Flat-panel display technology, ULSI device and technology, nano device and technology, solar cell, power semiconductor device
Course
Integarted Circuit process and device, Modern physics, Semiconductor device processing, Solid state electronics, Memory IC technology, Advanced Electromagnetics

Record
2001.02
~
迄今 Professor
1996.08
~
2001.01 Associate professor
1994.06
~
1996.07 Mosel Vitelic Inc. Dept. TD
Honor & Awards

Research

Research Achievement
Journal
[1] 57. M. H. Juang, J. Yu, C. C. Hwang, D. C. Shye, J. L. Wang, “Trench MOS barrier Schottky rectifier formed by counter-doping trench bottom implantation”, Microelectronics Reliability, in press, 2010.
[2] 56. M. H. Juang, Y. S. Peng, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer”, Microelectronics Engineering, in press, 2010.
[3] 55. M. H. Juang, Y. S. Peng, J. L. Wang, D. C. Shye, C. C. Hwang, and S. L. Jang, “Submicron-meter polycrystalline-SiGe thin-film transistors with tunneling field-effect-transistor structure”, Solid State Electronics, vol. 54, in press, 2010.
[4] 54. M. H. Juang, Y. S. Peng, J. L. Wang, D. C. Shye, C. C. Hwang, and S. L. Jang, “Microcrystalline-Si thin film transistors formed by using palladium silicided source/drain contact electrode”, Solid State Electronics, vol. 54, in press, 2010.
[5] 53. M. H. Juang, C. N. Lu, S. L. Jang, and H. C. Cheng, “Study of ultra-shallow p+n junctions formed by excimer laser annealing”, Material Chemistry and Physics, vol. 123, pp. 280-263, 2010.
[6] 52. M. H. Juang, C. W. Chang, D. C. Shye, C. C. Hwang, J. L. Wang, and S. L. Jang, “A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors”, Journal of Semiconductors, vol. 31, 064003, 2010.
[7] 51. M. H. Juang, C. W. Chang, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Study of polycrystalline-Si thin film transistors with different channel layer thickness at low bias voltage”, Microelectronics Engineering, vol. 87, pp. 1896-1900, 2010.
[8] 50. S. L. Jang, C. C. Shih, C. C. Liu, and M. H. Juang, “A 0.18 um CMOS Quadrature VCO using the quadruple push-push technique”, IEEE Microwave and Wireless Component Lett., vol. 20, pp. 343-345, 2010.
[9] 49. M. H. Juang, C. C. Hwang, D. C. Shye, J. L. Wang, and S. L. Jang, “Formation of 30-V power DMOSFET’s by implementing p-counter-doped region within n-type drift layer”, Solid State Electronics, vol. 54, pp. 724-727, 2010.
[10] 48. S. L. Jang, C. C. Liu, Y. J. Song, and M. H. Juang, ”A low voltage balanced clapp VCO in 0.13 micromolar CMOS technology”, Microwave and Optical Technology Lett., vol. 52, pp. 1623-1625, 2010.
[11] 47. S. L. Jang, J. J. Chen, C. C. Liu, and M. H. Juang, ” Injection-Locked frequency tripler with series-tuned resonator in 0.13μm CMOS technology”, Microwave and Optical Technology Lett., vol. 52, pp. 1107-1110, 2010.
[12] 46. M. H. Juang, P. S. Hu, and S. L. Jang, “Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure”, Thin Solid Films, vol. 518, pp. 3978-3981, 2010.
[13] 45. M. H. Juang, C. W. Chang, J. L. Wang, D. C. Shye, C. C. Hwang, and S. L. Jang, “Formation of n-channel polycrystalline-Si thin film transistors by dual source/drain implantation”, Solid State Electronics, vol. 54, pp. 516-519, 2010.
[14] 44. M. H. Juang, C. W. Chang, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Formation of sub-micrometer polycrystalline-SiGe thin film transistors by using a thinned channel layer”, Solid State Electronics, vol. 54, pp. 303-306, 2010.
[15] 43. M. H. Juang, C. W. Huang,, M. L. Wu, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation”, Microelectronics Engineering, vol. 87, pp. 620-623, 2010.
[16] 42. C. C. Liu, S. L. Jang, J. J. Chen, and M. H. Juang, “A 0.6-V low-power Armstrong VCO in 0.18 ?m CMOS”, Microwave and Optical technology Lett., vol. 52, pp. 116-119, 2010.
[17] 41. S. L. Jang, C. W. Lin, C. C. Liu, and M. H. Juang, “Tail-injected divide-by-4 qadrature injection locked frequency divider”, Inter. J. Electronics, vol. 96, pp. 1225-1235, 2009.
[18] 40. S. L. Jang, J. Y. Wun, C. C. Liu, and M. H. Juang, “A low power LC-tank SiGe BiCMOS injection locked frequency divider”, Microwave and Optical technology Lett., vol. 51, pp. 1970-1973, 2009.
[19] 39. S. L. Jang, C. C. Lin, S. H. Huang, and M. H. Juang, “Quadrature cross-coupled VCO implemented with body injection-locked frequency divider”, Microwave and Optical technology Lett., vol. 51, pp. 1918-1921, 2009.
[20] 38. M. H. Juang, C. W. Huang, C. W. Chang, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “The formation of polycrystalline-Si thin-film-transistors by using large-angle- tilt implantation of dopant through gate sidewall spacer ”, Solid State Electronics, vol. 53, pp. 1036-1040, 2009.
[21] 37. S. L. Jang, C. H. Yang, C. C. Liu, and M. H. Juang, “A wide-locking range 6-phase divide-by-3 injection-locked frequency divider”, Inter. J. Electronics, vol. 96, pp. 691-697, 2009.
[22] 36. S. L. Jang, K. C. Shen, C. W. Chang, and M. H. Juang, “A six-phase divide-by-3 injection-locked frequency divider in SiGe BiCMOS technology”, Microwave and Optical technology Lett., vol. 51, pp. 1555-1557, 2009.
[23] 35. S. L. Jang, R. K. Yang, C. W. Chang, and M. H. Juang, “ Multi-modulus LC injection-locked frequency dividers using single-ended injection”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 311-313, 2009.
[24] 34. S. L. Jang, C. W. Chang, W. C. Cheng, and M. H. Juang, “Low-power divide-by-3 injection-locked frequency dividers implemented with injection transformer”, Electronic Lett., vol. 45, pp. 240-241, 2009.
[25] 33. S. L. Jang, C. C. Liu, C. Y. Wu, and M. H. Juang, “A 5.6 GHz power balanced VCO in 0.18 ?m CMOS”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 233-235, 2009.
[26] 32. S. L. Jang, S. S. Huang, C. F. Lee, and M. H. Juang, “CMOS Colpitts quadrature VCO using the body injection-locked coupling technique”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 230-232, 2009.
[27] 31. M. H. Juang, S. H. Cheng, and S. L. Jang, “Formation of polycrystalline-Si thin-film-transistors with a retrograde channel doping profile”, Solid State Electronics, vol. 53, pp.371-375, 2009.
[28] 30. M. H. Juang P. S. Hu, and S. L. Jang, “Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate”, Semi. Sci. Technol., vol. 24, 025019(4pp), 2009.
[29] 29. S. L. Jang, C. W. Lin, C. C. Liu, and M. H. Juang, “An active-inductor injection locked frequency divider with variable division ratio”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 39-41, 2009.
[30] 28. S. L. Jang, S. S. Huang, C. F. Lee, and M. H. Juang, “ CMOS Quadrature VCO implemented with two first-harmonic injection-locked oscillators”, IEEE Microwave and Wireless Component Lett., vol. 18, pp. 695-697, 2008.
[31] 27. M. H. Juang, I. S. Tsai, and S. L. Jang, “The formation of polycrystalline-Si thin-film transistors with a thinned channel layer”, Semi. Sci. Technol., vol. 23, 105003(4pp), 2008.
[32] 26. S. L. Jang, S. H. Huang, C. F. Lee, and M. H. Juang, “ LC-tank Colpitts injection-locked frequency divider with record locking range”, IEEE Microwave and Wireless Component Lett., vol. 18, pp. 560-562, 2008.
[33] 25. S. L. Jang, S. C. Wu, C. F. Lee, and M. H. Juang, “CMOS top-series coupling quadrature injection-locked frequency divider”, Microwave and Optical technology Lett., vol. 50, pp. 2554-2557, 2008.
[34] 24. S. L. Jang, P. X. Lu, C. F. Lee, and M. H. Juang, “Divide-by-3 LC injection locked frequency divider with a transformer as an injector’s load”, Microwave and Optical technology Lett., vol. 50, pp. 2722-2725, 2008.
[35] 23. M. H. Juang, I. S. Tsai, S. L. Jang, and H. C. Cheng, “Formation of thin-film transistors with a polycrystalline hetero-structure channel layer”, Semi. Sci. Technol., vol. 23, 085017(4pp), 2008.
[36] 22. S. L. Jang, S. S. Huang, S. C. Wu, C. F. Lee, and M. H. Juang, “A low power X-band CMOS differential VCO”, Microwave and Optical technology Lett., vol. 50, pp. 1389-1391, 2008.
[37] 21. S. L. Jang, F. H. Chen, C. F. Lee, and M. H. Juang, “An LC-tank injection locked frequency divider with record locking range percentage”, Microwave and Optical technology Lett., vol. 50, pp. 808-810, 2008.
[38] 20. S. L. Jang, W. H. Yeh, C. F. Lee, and M. H. Juang, “A low power CMOS divide-by-3 LC-tank injection locked frequency divider”, Microwave and Optical technology Lett., vol. 50, pp. 259-263, 2008.
[39] 19. M. H. Juang C. L. Chen, and S. L. Jang, “A study of shallow trench isolation by using a ploy-Si sidewall buffer layer”, Semi. Sci. Technol., vol. 23, 015002(4pp), 2008.
[40] 18. C. F. Lee, S. L. Jang, and M. H. Juang, “ A wide locking range differential Colpitts injection locked frequency divider”, IEEE Microwave and Wireless Component Lett., vol. 17, pp. 790-792, 2007.
[41] 17. S. L. Jang, C. Y. Lin, C. F. Lee, and M. H. Juang, “A complementary Hartley injection-locked frequency dividers”, Microwave and Optical technology Lett., vol. 49, pp. 2817-2820, 2007.
[42] 16. S. H. Lee, S. L. Jang, C. F. Lee, and M. H. Juang, “Wide locking range divide-by-4 injection locked frequency dividers”, Microwave and Optical technology Lett., vol. 49, pp. 1533-1536, 2007.
[43] 15. S. H. Lee, S. L. Jang, Y. H. Chuang, J. J. Chao, J. F. Lee, and M. H. Juang, “A low power injection locked LC-tank oscillator with current reused topology”, IEEE Microwave and Wireless Component Lett., vol. 17, pp. 220-221, 2007.
[44] 14. Y. H. Chuang, S. H. Lee, S. L. Jang, and M. H. Juang, “A low-voltage quadrature CMOS VCO based on voltage-voltage feedback topology”, IEEE Microwave and Wireless Component Lett., vol. 16, pp. 696-698, 2006.
[45] 13. Y. H. Chuang, S. H. Lee, S. L. Jang, J. J. Chao, and M. H. Juang, “A ring-oscillator-based wide locking range frequency divider”, IEEE Microwave and Wireless Component Lett., vol. 16, pp. 470-471, 2006.
[46] 12. Y. H. Chuang, S. H. Lee, R. H. Yen, S. L. Jang, and M. H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider”, IEEE Microwave and Wireless Component Lett., vol. 16, pp. 299-301, 2006.
[47] 11. M. H. Juang W. C. Chueh, and S. L. Jang, “The formation of trench-gate power MOSFETs with a SiGe channel region”, Semi. Sci. Technol., vol. 21, pp. 709-802, 2006.
[48] 10. M. H. Juang, T. Y. Lin, and S. L. Jang, “The formation of Mo gate electrode with adjustable work function on thin Ta2O5 high-k dielectric films ”, Solid State Electronics, vol. 50, pp. 114-118, 2006.
[49] 9. M. H. Juang and Y. M. Chiu, “Effects of a lightly-doped-drain (LDD) implantation condition on the device characteristics of poly-Si thin-film-transistors”, Semi. Sci. Technol., vol. 21, pp. 291-294, 2006.
[50] 8. M. H. Juang and Y. M. Chiu, “High-performance poly-Si thin-film-transistors formed by using large-angle-tilt implanted drain”, Semi. Sci. Technol., vol. 20, pp. 1223-1225, 2005.
[51] 7. Heng-Fa Teng, S.-L. Jang , and M. H. Juang, " Modeling of Degradation Effects on the High Frequency Noise of Metal-Oxide-Semiconductor Field-Effect Transistors”, Japan Journal Applied Physics, vol. 44, pp. 38-43, 2005.
[52] 6. M. H. Juang, W. T. Chen, C. I. Ou-Yang, and S. L. Jang, M. J. Lin, and H. C. Cheng, “Fabrication of trench-gate power MOSFETs by using a dual doped body region”, Solid State Electronics, vol. 48, pp. 1079-1085, 2004.
[53] 5. H. F. Teng, S. L. Jang, and M. H. Juang, “A unified model for high-frequency current noise of MOSFETs”, Solid State Electronics, vol. 47, pp. 2043-2048, 2003.
[54] 4. D. C. Shye, C. C. Hwang, M. J. Lai, C. C. Jaing, J. S. Chen, S. Huang, M. H. Juang, B. S. Chiou, and H. C. Cheng, “Effects of post-oxygen treatment on Pt/(Ba,Sr)TiO3/Pt capacitors at low substrate temperatures”, Jpn. J. Appl. Phys., vol. 42, pp. 549-553, 2003.
[55] 3. M. H. Juang, C. I. Ou-Yang, and S. L. Jang, “A design consideration of channel doping profile for sub-0.12 mm partially depleted SOI n-MOSFET’s”, Solid State Electronics, vol. 46, pp. 1117-1121, 2002.
[56] 2. M. H. Juang, L. C. Sun, W. T. Chen, and C. I. Ou-Yang, “A process simplification scheme for fabricating self-aligned silicided trench-gate power MOSFET’s”, Solid State Electronics, vol. 45, pp. 169-172, 2001.
[57] 1. C. C. Hwang, M. H. Juang, M. J. Lai, C. C. Jaing, J. S. Chen, S. Huang, and H. C Cheng, “Effect of rapid-thermal-annealed TiN barrier layer on the Pt/BST/Pt capacitors prepared by RF magnetron cosputter technique at low substrate temperatures”, Solid State Electronics, vol. 45, pp. 121-125, 2001.
Conference
[1] 11. Yun-Hsueh Chuang, Shao-Hua Lee, Chien-Feng Lee, Sheng-Lyang Jang , and Miin-Horng Juang., " A new CMOS VCO topology with capacitive degeneration and transformer feedback,” 2006 VLSI- DAT, Taiwan.
[2] 10. Y.-H. Chuang, S.-L. Jang,, W.-C. Huang, S.-H. Lee, and M.-H. Juang, "A Wide-Band fully-integrated CMOS oscillator Tuned by voltage Controlled transformer,” 1st applied science and technology conference(ASTC)-photonics and communications, B02, 2004, Kaohsiung, Taiwan.
[3] 9. C.I. Ou-Yang and M. H. Juang, “Optimal design of trench-type insulated gate bipolar transistors with a blocking voltage over 600 volts”, Inter. Electron Devices and Mater. Symp., Hsin-chu, Taiwan, 2004.
[4] 8. M. H. Juang, W. T. Chen, C. I. Ou-Yang, S. L. Jang, and H. C. Cheng, “Fabrication of trench-gate power MOSFET’s by using a dual doped body region”, Electron Devices and Mater. Symp., Kee-Lung, Taiwan, 2003.
[5] 7. M. H. Juang and C. L. Chen, “Improvement of shallow trench isolation technology by using a poly-Si buffer layer”, International Electron Devices and Mater. Symp., Taipei, Taiwan, 2002.
[6] 6. M. H. Juang and C. N. Lu, “Effect of post low-temperature treatment on shallow p+n junction formed by excimer laser annealing”, International 9th symposium on Nano Device Technology, Hsinchu, Taiwan,, 2002.
[7] 5. M. H. Juang, C. C. Hwang, and H. C. Cheng, “Effect of RTA on TiN Films as the barrier layer for Pt/BST/Pt capacitors prepared by RF magnetron co-sputter technique at low substrate temperature”, Proceeding of Mater. Res. Symp. Spring Meeting, San Francisco, U.S.A., 2000 (acceptation for publication in 2002).
[8] 4. M. H. Juang and C. N. Lu, “Study of forming shallow p+n junctions using excimer laser annealing”, Electron Devices and Mater. Symp., , Taiwan, 2001.
[9] 3. M. H. Juang, C. C. Hwang, and H. C. Cheng, “Effects of post oxygen plasma treatment on Pt/(Ba,Sr)TiO3/Pt capacitors at low substrate temperatures”, International Conference on Solid State and Integrated Circuit Technology, ShangHai, China, 2001.
[10] 2. M. H. Juang, C. I. Ou-Yang, and C. T. Lin, “Improvement of thin palladium silicde films by incorporating phosphorus dopant”, Proceeding of Mater. Res. Symp. Fall Meeting, Boston, U.S.A., 2000 (acceptation for publication in 2001).
[11] 1. M. H. Juang, C. C. Hwang, and H. C. Cheng, “Effect of RTA on TiN Films as the barrier layer for Pt/BST/Pt capacitors prepared by RF magnetron co-sputter technique at low substrate temperature”, Mater. Res. Symp., Spring Meeting, , San Francisco, U.S.A., 2001.
Patent
Book
Other

Project
Title Total Amount Excution Duration Client
A study of Si-based solar cell structure 573,000 96 - 97 NSC
Design and fabrication of microcrystalline thin-film transistors at ultra low-temperature process 885,000 0000-00-00 - 0000-00-00 NSC

Student
Ph.D
92
Application design of Si MOSFET on deep submicron ans power ICs
C. I. Ou-Yang
M.S
100
Study of poly-Si thin-film-transistors with large angle tilt implanted drain region
Yen-ming Chen
100
Implementation of CRLH Dual-band VCO and Novel VCOs using Transformer Coupling
You-Wei Liu
100
Design of Buck Converters with Dual-Path Capacitor Multiplier Technique
Chih-yao Hsu
100
Study of Lateral Power MOSFET with Sub-gate Structure
Ting-you Guo
99
Reserch of 0.3V Voltage-Controlled Oscillator And High Performance Quadrature Voltage-Controlled Oscillator
Meng-hsin Chen
99
Design of 100-nm Tunneling Field-Effect Transistor
Shih-yuan Huang
99
Study of Tunneling-Field-Effect Poly-Si Thin-Film-Transistors
Ping-Jung Liu
99
Study of La0.7Sr0.3MnO3 thin film applied on micro-thermistor sensor
juei-chun Wang
99
Composite Insulated Gate Bipolar Transistor Device With Series Depletion-mode Poly-Si TFT
Chi-Ju Hsieh
98
溝渠式金氧半蕭特基整流器之特性研究
于鑫龍
98
0.18 μm CMOS 製程之低電壓壓控震盪器之研製
廖英翔
98
新型四相位壓控振盪器與注入鎖定除頻器之設計
陳漢昇
98
CMOS電壓控制振盪器與SiGe注入鎖定除頻器之研製
王承慈
97
陷阱分佈對矽太陽電池特性影響之研究
劉哲孝
97
使用MEMS電感之壓控振盪器及注入鎖定除頻器之設計
溫俊彥
97
多晶矽光二極體與光電晶體之研究
張明全
97
複晶矽薄膜電晶體之結構設計
張家偉
96
光電晶體元件結構設計之研究
陳哲豪
96
新式四相位壓控振盪器及注入鎖定除頻器之設計
黃世新
96
注入鎖定除頻器及壓控震盪器之設計與實作
吳俊毅
96
新型多模注入鎖定除頻器與串疊型電壓控制振盪器之設計
楊昌昊
96
Design and Implementation of Injection-Locked Frequency Divider
Chi-Wen Lin
95
Study of Tunneling field effect transistor
B. S. Hu
95
Study of heterostructure poly-Si/SiC TFT
I. S. Tsai
94
Study of Si-based solar cell
H. Y. Juang
94
Study of buried channel TFT
M. L. Wu
93
Study of Channel engineering in poly-Si thin-film-transistors
S. H. Cheng
93
Device design of sub-0.1um MOSFETs
C. S. Yang
93
Study of drain engineering in poly-Si thin-film-transistors
Y. M. Chiu
93
Study and fabrication of Si nanowires
D. L. Lee
92
Study of adjustable work function gate electrode on high-k dielectrics in nanotechnology devices
T. Y. Lin
92
Design of high-performance IGBT
C. C. Lai
91
Optimal design of SiGe channel trench-gate power MOSFET
W. C. Chueh
Student's Project
93
Simulation design of Si solar cell
G. D. Lin
91
Study of characteristics of heterostructure transistor
M. L. Wu
89
Study and simualtion of Lateral IGBT
J. H. Chen
Student's Honor