Faculty

Yung-Hui Chung Associate Professor
photo
Position
Associate Professor
Education
PhD., Electronics Engineering, National Chiao-Tung University 
E-mail
yhchung@mail.ntust.edu.tw
Room
EE 601-2
Office hour
Wednesday, 09:00~12:00
Telephone
886-2-27376394
FAX
886-2-27376424
Homepage
Laboratory
Mixed-Signal IC Laboratory (EE601-2)
Major Field
Analog/Mixed-signal IC Design, Data Conversion Circuits, Digital Calibration Circuits, Biomedical Analog Front-End Circuits, Phase-Locked Loops
Course
VLSI Data Conversion Circuits, Introduction to Analog Circuit Design, Analog Circuit Design Practice, Integrated Circuit Layout Practice

Record
2017.08
~
Now Associate Professor, DECE, NTUST
2012.09
~
2017.07 Assistant Professor, DECE, NTUST
2010.07
~
2012.08 Technical Manager, MediaTek Inc.
2000.10
~
2003.10 Technical Manager, Faraday Tech.
1999.05
~
2000.07 Senior Engineer, Global UniChip
1998.03
~
1999.05 Engineer, ERSO, ITRI
1994.10
~
1998.03 Engineer, OES, ITRI
Honor & Awards
1994
斐陶斐學會榮譽會員

Research

Research Achievement
Journal
[1] Yung-Hui Chung* and Ya-Mien Hsu, "A 12-bit 100-MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme" accepted by IEEE Trans. Circuits Syst. II, Exp. Briefs.
[2] Yung-Hui Chung*, Chia-Wei Yen, Pei-Kang Tsai, and Pei-Kang Tsai, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme,” IEEE Trans. on VLSI Systems, vol. 26, no. 10, pp. 1989-1998, Oct. 2018.
[3] Yung-Hui Chung*, Chia-Wei Yen, and Pei-Kang Tsai, "A 12-bit 10-MS/s SAR ADC with a Binary-Window DAC Switching Scheme in 180-nm CMOS," International Journal of Circuit Theory and Applications, vol. 46, no. 4, pp. 748-763, Apr. 2018. https://doi.org/10.1002/cta.2424
[4] Yung-Hui Chung*, Wei-Shu Rih, and Che-Wei Chang, "A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 8, pp.999-1003, Aug. 2018.
[5] Yung-Hui Chung*, Cheng-Hsun Tsai, and Hsuan-Chih Yeh, "A 5-bit 1-GS/s Binary-Search ADC in 90-nm CMOS," Microelectronics Journal, vol. 63, pp.131-137, Apr. 2017
[6] Yung-Hui Chung* and Chia-Wei Yen, "An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS," IEEE Trans. on VLSI Systems, vol. 25, no. 12, pp. 3434-3443, Dec. 2017.
[7] Yung-Hui Chung*, Chia-Wei Yen, and Meng-Hsuan Wu, "A 24-uW 12-b 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS," IEEE Trans. on VLSI Systems, vol. 24, no. 11, pp. 3334-3344, Nov. 2016.
[8] Yung-Hui Chung* and Jieh-Tsorng Wu, “A 16-mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” IEEE Trans. on VLSI Systems, vol. 23, no. 3, pp. 557-566, Mar. 2015.
[9] Yung-Hui Chung*, Meng-Hsuan Wu and Hung-Sung Li, "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," IEEE Trans. on Circuits and Systems I, vol. 62, no. 1, pp.10-18, Jan. 2015.
[10] Yung-Hui Chung* and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2217–2226, Nov., 2010.
Conference
[1] Yung-Hui Chung and Min-Sheng Chiang, "A 12-bit Synchronous-SAR ADC for IoT Applications," to appear in IEEE ISCAS 2019.
[2] Yung-Hui Chung, Hsuan-Chih Yeh, and Che-Wei Chang, 'A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS,' in Proc. of IEEE International Symposium on Next Generation Electronics (ISNE), May 2018, pp.1-2.
[3] Yung-Hui Chung, Chia-Yi Hu, and Che-We Chang, “A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2018, pp. 243–246.
[4] Yung-Hui Chung, Hung-Po Ni, Yi-Shen Lin, and Qi-Feng Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018, pp.34-37.
[5] Yung-Hui Chung* and Hua-Wei Tseng, “A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS,” in Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Oct. 2017, pp. 1-2.
[6] Yung-Hui Chung and Song-Yo Shih, “A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2017, pp. 1-4.
[7] Yung-Hui Chung and Wei-Shu Rih, “A 6-bit 1.6-GS/s Domino-SAR ADC in 55nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 216-217.
[8] Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih, “A 12-bit 160-MS/s Ping-Pong Subranged-SAR ADC in 65nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 5-6. (Best Paper Award)
[9] Yung-Hui Chung and Chia-Wei Yen, "A PVT-Tracking Metastability Detector for Asynchronous ADCs," in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2016, pp.1462-1465.
[10] Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s Binary-Search ADC in 90nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, pp.334-337.
[11] Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS," in Proc. IEEE SOC Conference, pp. 25-29, Sep. 2015.
[12] Yung-Hui Chung, “Perturbation-Based Digital Background Calibration Technique for Pipelined ADCs,” in Proc. of IEEE Int. Sym. on Circuits and Systems (ISCAS), 2014.
[13] Yung-Hui Chung, Meng-Hsuan Wu, and Hung-Sung Li, “A 24uW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2013.
[14] Yung-Hui Chung, “The Swapping Binary-Window DAC Switching Technique for SAR ADCs,” in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2013, pp.2231-2234.
[15] Meng-Hsuan Wu, Yung-Hui Chung and Hung-Sung Li, “A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2012, pp. 157-160.
[16] Yung-Hui Chung and Jieh-Tsorng Wu, “A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” in VLSI Circuits Symp. Dig., Jun. 2011, pp. 128–129.
[17] Yung-Hui Chung and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2009, pp. 137–140.
Patent
[1] Yung-Hui Chung and Bo-Wei Chen, "Successive approximation register analog-to-digital converter and method for operating the same," US Patent 10,211,847
[2] Yung-Hui Chung and Bo-Wei Chen, "Signal comparison apparatus and method of controlling same," US Patent 9,395,746
[3] Meng-Hsuan Wu and Yung-Hui Chung,"SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF," US Patent 8,508,400
[4] Yung-Hui Chung, "METHOD AND APPARATUS FOR PERFORMING NONLINEARITY CALIBRATION," US Patent 8,525,711
[5] Yung-Hui Chung and Meng-Hsuan Wu, "Successive approximation register analog-digital converter and method for operating the same," US Patent 8,599,059
Book
[1] Yung-Hui Chung, Chia-Wei Yen, and Cheng-Hsun Tsai, "A 12-bit 1-MS/s 26-uW SAR ADC for Sensor Applications," in Nano Devices and Sensors, pp.137-162, 2016, De Gruyter.
Other

Project
Title Total Amount Excution Duration Client
Design and Analysis of Digital Calibration Techniques for ultra-high resolution SAR ADCs 新台幣700,000元整 108 - 108 CCL/ITRI
Calibration Techniques in a 16-bit SAR ADC 新台幣700,000元整 107 - 107 CCL/ITRI
16 bit 1 MS/s SAR ADC 新台幣900,000元整 106 - 106 ITRI
14-bit High-Speed ADCs for Next-Generation Ultrasonic and Communication Systems 新台幣2,544,000元整 106 - 109 MOST
Research of a high-speed and high-resolution ADC architecture 新台幣700,000元整 105 - 105 CCL/ITRI
Research of a high-speed and high-resolution ADC architecture 新台幣700,000元整 104 - 104 ITRI
Analog-to-Digital Converters for Advanced Measuring Instruments 新台幣 2,379,000元整 103 - 106 NSC
A 12-bit 100-MS/s ADC for Ultrasound AFE 新台幣700,000元整 103 - 103 ITRI
Research of a high-speed and high-resolution ADC architecture 新台幣700,000元整 102 - 102 ITRI
High-Efficiency 12-bit Successive-Approximation Register Analog-to-Digital Converter Design 新台幣1,800,000元整 101 - 103 NSC

Student
Ph.D
M.S
107
Low Jitter PLL Design Techniques
馬世為
107
A 14b 1-GS/s TI Calibration ADC
邱慶秦
107
Noise-Shaping SAR ADC
林仕祥
107
A 10b 5GS/s TI-SAR ADC
吳道展
106
A 16b Calibration SAR ADC
曾啟峰
106
A Low-Jitter Multi-Phase Clock Generation Circuits
黃弘鈞
105
A 12-bit Window-SAR ADC
江民陞
105
A 14-bit 150-MS/s Calibration ADC
Eason Lin
105
A 10b 400-MS/s SAR ADC
Edward Lai
104
A 16-bit 1-MS/s Calibration-Free SAR ADC
Vic Tian
104
A 12-bit 250-MS/s Subranged-SAR ADC
Rih, Wei-Shu
104
An 8-bit 1.25-GS/s SAR ADC
Chang, Che-Wei
103
Design and Implementation of 2b/Cycle-Based 10-bit High-Speed SAR ADCs (Graduated, FocalTech)
Tseng, Hua-Wei
103
Design of a Timing Skew Calibration Processor for High-Speed Time-Interleaved ADCs (Graduated, Realtek)
Hu, Chia-Yi
103
A 12-bit 100-MS/s SAR ADC (Graduated, Elite Tech)
Hsu, Ya-Mien
103
A 14-bit Analog-to-Digital Converter with Background Nonlinearity Calibration Technique (Graduated, ALi Tech)
Andrew Lee
103
Design and Implementation of 12-bit SAR ADCs with Binary-Window DAC Switching Technique (Graduated)
Paul Ni
102
An 8-bit 1.25-GS/s ADC (Graduated, FocalTech)
Tsai, Cheng-Hsun
102
A 12-bit 100-MS/s SAR ADC (Graduated)
Yen, Chia-Wei
102
A 12-bit 100-MS/s ADC (Graduated, ICL/ITRI)
Shih, Song-You
102
A 10-bit 160-MS/s ADC (Graduated, UMC)
Yeh, Hsuan-Chih
Student's Project
108
A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time
陳品豪、吳昇翰
108
Capacitorless Self-Clocked All-Digital Low-Dropout Regulator
余心豪、賴冠衡
108
Switched Capacitor based High Positive and Negative Voltage Charge-pump
林賢順、蔡旻修、何宗翰
107
Bandgap Reference Circuits: Group-2
謝昱廷,莊懿
107
Bandgap Reference Circuits: Group-1
林惟鍾,林巨彥
107
Analog and digital circuit implementation
王挺安、蕭靖燁
106
Bandgap Reference and Regulators
周郁桀、邵丞擇、馬世為
105
A 10-bit 100-KS/s SAR ADC
賴冠亨、李榮章
105
A biomedical analog front-end (AFE) circuit: IA + PGA
邱宥榮、游景賀
105
A LDO regulator for biomedical AFE circuits
曾俊銘、江振忠
105
A bandgap circuit design
葉建祖
105
An analog front-end (receiver) circuits for logic analyzers (LAs)
洪宇廷
104
A 10-bit 100-MS/s SAR ADC
池振聖、侯人文
104
A 10-bit 1-MS/s SAR ADC
胡家瑋、朱致緯
104
Bandgap Reference Circuits
簡國訓、黃林育麟
104
ADC and IA Testing
林道、黃金增
103
Energy Harvesting System Design
黃揚景、林鈺翔
103
Biomedical Sensing System Design
唐煜杰、劉建宏
103
High-Speed Instrumentation AFE Circuit Design
鄧逸祥
102
Biomedical Analog Front-End Circuit Design
洪瑋謙, 張振誠
102
12-bit Digital-to-Analog Conversion Circuit Design
David Yang
101
Biomedical Sensing System Design
孫以諾,謝曜竹,任欣圻
Student's Honor