教師資料

莊敏宏 Miin-Horng Juang
職稱
特聘教授
學歷
國立交通大學電子研究所博士
電子郵件
AK80492@mail.ntust.edu.tw
辦公室
EE 705-1

Office Hours Mon. 12:00~13:30 Thr. 12:00~13:30
電話 886-2-27376436
傳真
個人網頁 N/A
實驗室 元件/製程實驗室
研究領域 平面顯示器技術、積體電路元件及技術、奈米元件及技術、太陽電池、功率元件
開授課程 積體電路製程與元件、近代物理、半導體元件製程、固態電子學、記憶體技術、高等電磁學、電子元件特論

2001.02 ~  迄今 教授
1996.08 ~  2001.01 副教授
1994.06 ~  1996.07 台灣茂矽電子技術開發處



研究成果
  [1]   57. M. H. Juang, J. Yu, C. C. Hwang, D. C. Shye, J. L. Wang, “Trench MOS barrier Schottky rectifier formed by counter-doping trench bottom implantation”, Microelectronics Reliability, in press, 2010.
  [2]   56. M. H. Juang, Y. S. Peng, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer”, Microelectronics Engineering, in press, 2010.
  [3]   55. M. H. Juang, Y. S. Peng, J. L. Wang, D. C. Shye, C. C. Hwang, and S. L. Jang, “Submicron-meter polycrystalline-SiGe thin-film transistors with tunneling field-effect-transistor structure”, Solid State Electronics, vol. 54, in press, 2010.
  [4]   54. M. H. Juang, Y. S. Peng, J. L. Wang, D. C. Shye, C. C. Hwang, and S. L. Jang, “Microcrystalline-Si thin film transistors formed by using palladium silicided source/drain contact electrode”, Solid State Electronics, vol. 54, in press, 2010.
  [5]   53. M. H. Juang, C. N. Lu, S. L. Jang, and H. C. Cheng, “Study of ultra-shallow p+n junctions formed by excimer laser annealing”, Material Chemistry and Physics, vol. 123, pp. 280-263, 2010.
  [6]   52. M. H. Juang, C. W. Chang, D. C. Shye, C. C. Hwang, J. L. Wang, and S. L. Jang, “A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors”, Journal of Semiconductors, vol. 31, 064003, 2010.
  [7]   51. M. H. Juang, C. W. Chang, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Study of polycrystalline-Si thin film transistors with different channel layer thickness at low bias voltage”, Microelectronics Engineering, vol. 87, pp. 1896-1900, 2010.
  [8]   50. S. L. Jang, C. C. Shih, C. C. Liu, and M. H. Juang, “A 0.18 um CMOS Quadrature VCO using the quadruple push-push technique”, IEEE Microwave and Wireless Component Lett., vol. 20, pp. 343-345, 2010.
  [9]   49. M. H. Juang, C. C. Hwang, D. C. Shye, J. L. Wang, and S. L. Jang, “Formation of 30-V power DMOSFET’s by implementing p-counter-doped region within n-type drift layer”, Solid State Electronics, vol. 54, pp. 724-727, 2010.
  [10]   48. S. L. Jang, C. C. Liu, Y. J. Song, and M. H. Juang, ”A low voltage balanced clapp VCO in 0.13 micromolar CMOS technology”, Microwave and Optical Technology Lett., vol. 52, pp. 1623-1625, 2010.
  [11]   47. S. L. Jang, J. J. Chen, C. C. Liu, and M. H. Juang, ” Injection-Locked frequency tripler with series-tuned resonator in 0.13μm CMOS technology”, Microwave and Optical Technology Lett., vol. 52, pp. 1107-1110, 2010.
  [12]   46. M. H. Juang, P. S. Hu, and S. L. Jang, “Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure”, Thin Solid Films, vol. 518, pp. 3978-3981, 2010.
  [13]   45. M. H. Juang, C. W. Chang, J. L. Wang, D. C. Shye, C. C. Hwang, and S. L. Jang, “Formation of n-channel polycrystalline-Si thin film transistors by dual source/drain implantation”, Solid State Electronics, vol. 54, pp. 516-519, 2010.
  [14]   44. M. H. Juang, C. W. Chang, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Formation of sub-micrometer polycrystalline-SiGe thin film transistors by using a thinned channel layer”, Solid State Electronics, vol. 54, pp. 303-306, 2010.
  [15]   43. M. H. Juang, C. W. Huang,, M. L. Wu, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation”, Microelectronics Engineering, vol. 87, pp. 620-623, 2010.
  [16]   42. C. C. Liu, S. L. Jang, J. J. Chen, and M. H. Juang, “A 0.6-V low-power Armstrong VCO in 0.18 ?m CMOS”, Microwave and Optical technology Lett., vol. 52, pp. 116-119, 2010.
  [17]   41. S. L. Jang, C. W. Lin, C. C. Liu, and M. H. Juang, “Tail-injected divide-by-4 qadrature injection locked frequency divider”, Inter. J. Electronics, vol. 96, pp. 1225-1235, 2009.
  [18]   40. S. L. Jang, J. Y. Wun, C. C. Liu, and M. H. Juang, “A low power LC-tank SiGe BiCMOS injection locked frequency divider”, Microwave and Optical technology Lett., vol. 51, pp. 1970-1973, 2009.
  [19]   39. S. L. Jang, C. C. Lin, S. H. Huang, and M. H. Juang, “Quadrature cross-coupled VCO implemented with body injection-locked frequency divider”, Microwave and Optical technology Lett., vol. 51, pp. 1918-1921, 2009.
  [20]   38. M. H. Juang, C. W. Huang, C. W. Chang, D. C. Shye, J. L. Wang, C. C. Hwang, and S. L. Jang, “The formation of polycrystalline-Si thin-film-transistors by using large-angle- tilt implantation of dopant through gate sidewall spacer ”, Solid State Electronics, vol. 53, pp. 1036-1040, 2009.
  [21]   37. S. L. Jang, C. H. Yang, C. C. Liu, and M. H. Juang, “A wide-locking range 6-phase divide-by-3 injection-locked frequency divider”, Inter. J. Electronics, vol. 96, pp. 691-697, 2009.
  [22]   36. S. L. Jang, K. C. Shen, C. W. Chang, and M. H. Juang, “A six-phase divide-by-3 injection-locked frequency divider in SiGe BiCMOS technology”, Microwave and Optical technology Lett., vol. 51, pp. 1555-1557, 2009.
  [23]   35. S. L. Jang, R. K. Yang, C. W. Chang, and M. H. Juang, “ Multi-modulus LC injection-locked frequency dividers using single-ended injection”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 311-313, 2009.
  [24]   34. S. L. Jang, C. W. Chang, W. C. Cheng, and M. H. Juang, “Low-power divide-by-3 injection-locked frequency dividers implemented with injection transformer”, Electronic Lett., vol. 45, pp. 240-241, 2009.
  [25]   33. S. L. Jang, C. C. Liu, C. Y. Wu, and M. H. Juang, “A 5.6 GHz power balanced VCO in 0.18 ?m CMOS”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 233-235, 2009.
  [26]   32. S. L. Jang, S. S. Huang, C. F. Lee, and M. H. Juang, “CMOS Colpitts quadrature VCO using the body injection-locked coupling technique”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 230-232, 2009.
  [27]   31. M. H. Juang, S. H. Cheng, and S. L. Jang, “Formation of polycrystalline-Si thin-film-transistors with a retrograde channel doping profile”, Solid State Electronics, vol. 53, pp.371-375, 2009.
  [28]   30. M. H. Juang P. S. Hu, and S. L. Jang, “Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate”, Semi. Sci. Technol., vol. 24, 025019(4pp), 2009.
  [29]   29. S. L. Jang, C. W. Lin, C. C. Liu, and M. H. Juang, “An active-inductor injection locked frequency divider with variable division ratio”, IEEE Microwave and Wireless Component Lett., vol. 19, pp. 39-41, 2009.
  [30]   28. S. L. Jang, S. S. Huang, C. F. Lee, and M. H. Juang, “ CMOS Quadrature VCO implemented with two first-harmonic injection-locked oscillators”, IEEE Microwave and Wireless Component Lett., vol. 18, pp. 695-697, 2008.
  [31]   27. M. H. Juang, I. S. Tsai, and S. L. Jang, “The formation of polycrystalline-Si thin-film transistors with a thinned channel layer”, Semi. Sci. Technol., vol. 23, 105003(4pp), 2008.
  [32]   26. S. L. Jang, S. H. Huang, C. F. Lee, and M. H. Juang, “ LC-tank Colpitts injection-locked frequency divider with record locking range”, IEEE Microwave and Wireless Component Lett., vol. 18, pp. 560-562, 2008.
  [33]   25. S. L. Jang, S. C. Wu, C. F. Lee, and M. H. Juang, “CMOS top-series coupling quadrature injection-locked frequency divider”, Microwave and Optical technology Lett., vol. 50, pp. 2554-2557, 2008.
  [34]   24. S. L. Jang, P. X. Lu, C. F. Lee, and M. H. Juang, “Divide-by-3 LC injection locked frequency divider with a transformer as an injector’s load”, Microwave and Optical technology Lett., vol. 50, pp. 2722-2725, 2008.
  [35]   23. M. H. Juang, I. S. Tsai, S. L. Jang, and H. C. Cheng, “Formation of thin-film transistors with a polycrystalline hetero-structure channel layer”, Semi. Sci. Technol., vol. 23, 085017(4pp), 2008.
  [36]   22. S. L. Jang, S. S. Huang, S. C. Wu, C. F. Lee, and M. H. Juang, “A low power X-band CMOS differential VCO”, Microwave and Optical technology Lett., vol. 50, pp. 1389-1391, 2008.
  [37]   21. S. L. Jang, F. H. Chen, C. F. Lee, and M. H. Juang, “An LC-tank injection locked frequency divider with record locking range percentage”, Microwave and Optical technology Lett., vol. 50, pp. 808-810, 2008.
  [38]   20. S. L. Jang, W. H. Yeh, C. F. Lee, and M. H. Juang, “A low power CMOS divide-by-3 LC-tank injection locked frequency divider”, Microwave and Optical technology Lett., vol. 50, pp. 259-263, 2008.
  [39]   19. M. H. Juang C. L. Chen, and S. L. Jang, “A study of shallow trench isolation by using a ploy-Si sidewall buffer layer”, Semi. Sci. Technol., vol. 23, 015002(4pp), 2008.
  [40]   18. C. F. Lee, S. L. Jang, and M. H. Juang, “ A wide locking range differential Colpitts injection locked frequency divider”, IEEE Microwave and Wireless Component Lett., vol. 17, pp. 790-792, 2007.
  [41]   17. S. L. Jang, C. Y. Lin, C. F. Lee, and M. H. Juang, “A complementary Hartley injection-locked frequency dividers”, Microwave and Optical technology Lett., vol. 49, pp. 2817-2820, 2007.
  [42]   16. S. H. Lee, S. L. Jang, C. F. Lee, and M. H. Juang, “Wide locking range divide-by-4 injection locked frequency dividers”, Microwave and Optical technology Lett., vol. 49, pp. 1533-1536, 2007.
  [43]   15. S. H. Lee, S. L. Jang, Y. H. Chuang, J. J. Chao, J. F. Lee, and M. H. Juang, “A low power injection locked LC-tank oscillator with current reused topology”, IEEE Microwave and Wireless Component Lett., vol. 17, pp. 220-221, 2007.
  [44]   14. Y. H. Chuang, S. H. Lee, S. L. Jang, and M. H. Juang, “A low-voltage quadrature CMOS VCO based on voltage-voltage feedback topology”, IEEE Microwave and Wireless Component Lett., vol. 16, pp. 696-698, 2006.
  [45]   13. Y. H. Chuang, S. H. Lee, S. L. Jang, J. J. Chao, and M. H. Juang, “A ring-oscillator-based wide locking range frequency divider”, IEEE Microwave and Wireless Component Lett., vol. 16, pp. 470-471, 2006.
  [46]   12. Y. H. Chuang, S. H. Lee, R. H. Yen, S. L. Jang, and M. H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider”, IEEE Microwave and Wireless Component Lett., vol. 16, pp. 299-301, 2006.
  [47]   11. M. H. Juang W. C. Chueh, and S. L. Jang, “The formation of trench-gate power MOSFETs with a SiGe channel region”, Semi. Sci. Technol., vol. 21, pp. 709-802, 2006.
  [48]   10. M. H. Juang, T. Y. Lin, and S. L. Jang, “The formation of Mo gate electrode with adjustable work function on thin Ta2O5 high-k dielectric films ”, Solid State Electronics, vol. 50, pp. 114-118, 2006.
  [49]   9. M. H. Juang and Y. M. Chiu, “Effects of a lightly-doped-drain (LDD) implantation condition on the device characteristics of poly-Si thin-film-transistors”, Semi. Sci. Technol., vol. 21, pp. 291-294, 2006.
  [50]   8. M. H. Juang and Y. M. Chiu, “High-performance poly-Si thin-film-transistors formed by using large-angle-tilt implanted drain”, Semi. Sci. Technol., vol. 20, pp. 1223-1225, 2005.
  [51]   7. Heng-Fa Teng, S.-L. Jang , and M. H. Juang, " Modeling of Degradation Effects on the High Frequency Noise of Metal-Oxide-Semiconductor Field-Effect Transistors”, Japan Journal Applied Physics, vol. 44, pp. 38-43, 2005.
  [52]   6. M. H. Juang, W. T. Chen, C. I. Ou-Yang, and S. L. Jang, M. J. Lin, and H. C. Cheng, “Fabrication of trench-gate power MOSFETs by using a dual doped body region”, Solid State Electronics, vol. 48, pp. 1079-1085, 2004.
  [53]   5. H. F. Teng, S. L. Jang, and M. H. Juang, “A unified model for high-frequency current noise of MOSFETs”, Solid State Electronics, vol. 47, pp. 2043-2048, 2003.
  [54]   4. D. C. Shye, C. C. Hwang, M. J. Lai, C. C. Jaing, J. S. Chen, S. Huang, M. H. Juang, B. S. Chiou, and H. C. Cheng, “Effects of post-oxygen treatment on Pt/(Ba,Sr)TiO3/Pt capacitors at low substrate temperatures”, Jpn. J. Appl. Phys., vol. 42, pp. 549-553, 2003.
  [55]   3. M. H. Juang, C. I. Ou-Yang, and S. L. Jang, “A design consideration of channel doping profile for sub-0.12 mm partially depleted SOI n-MOSFET’s”, Solid State Electronics, vol. 46, pp. 1117-1121, 2002.
  [56]   2. M. H. Juang, L. C. Sun, W. T. Chen, and C. I. Ou-Yang, “A process simplification scheme for fabricating self-aligned silicided trench-gate power MOSFET’s”, Solid State Electronics, vol. 45, pp. 169-172, 2001.
  [57]   1. C. C. Hwang, M. H. Juang, M. J. Lai, C. C. Jaing, J. S. Chen, S. Huang, and H. C Cheng, “Effect of rapid-thermal-annealed TiN barrier layer on the Pt/BST/Pt capacitors prepared by RF magnetron cosputter technique at low substrate temperatures”, Solid State Electronics, vol. 45, pp. 121-125, 2001.
  [1]   11. Yun-Hsueh Chuang, Shao-Hua Lee, Chien-Feng Lee, Sheng-Lyang Jang , and Miin-Horng Juang., " A new CMOS VCO topology with capacitive degeneration and transformer feedback,” 2006 VLSI- DAT, Taiwan.
  [2]   10. Y.-H. Chuang, S.-L. Jang,, W.-C. Huang, S.-H. Lee, and M.-H. Juang, "A Wide-Band fully-integrated CMOS oscillator Tuned by voltage Controlled transformer,” 1st applied science and technology conference(ASTC)-photonics and communications, B02, 2004, Kaohsiung, Taiwan.
  [3]   9. C.I. Ou-Yang and M. H. Juang, “Optimal design of trench-type insulated gate bipolar transistors with a blocking voltage over 600 volts”, Inter. Electron Devices and Mater. Symp., Hsin-chu, Taiwan, 2004.
  [4]   8. M. H. Juang, W. T. Chen, C. I. Ou-Yang, S. L. Jang, and H. C. Cheng, “Fabrication of trench-gate power MOSFET’s by using a dual doped body region”, Electron Devices and Mater. Symp., Kee-Lung, Taiwan, 2003.
  [5]   7. M. H. Juang and C. L. Chen, “Improvement of shallow trench isolation technology by using a poly-Si buffer layer”, International Electron Devices and Mater. Symp., Taipei, Taiwan, 2002.
  [6]   6. M. H. Juang and C. N. Lu, “Effect of post low-temperature treatment on shallow p+n junction formed by excimer laser annealing”, International 9th symposium on Nano Device Technology, Hsinchu, Taiwan,, 2002.
  [7]   5. M. H. Juang, C. C. Hwang, and H. C. Cheng, “Effect of RTA on TiN Films as the barrier layer for Pt/BST/Pt capacitors prepared by RF magnetron co-sputter technique at low substrate temperature”, Proceeding of Mater. Res. Symp. Spring Meeting, San Francisco, U.S.A., 2000 (acceptation for publication in 2002).
  [8]   4. M. H. Juang and C. N. Lu, “Study of forming shallow p+n junctions using excimer laser annealing”, Electron Devices and Mater. Symp., , Taiwan, 2001.
  [9]   3. M. H. Juang, C. C. Hwang, and H. C. Cheng, “Effects of post oxygen plasma treatment on Pt/(Ba,Sr)TiO3/Pt capacitors at low substrate temperatures”, International Conference on Solid State and Integrated Circuit Technology, ShangHai, China, 2001.
  [10]   2. M. H. Juang, C. I. Ou-Yang, and C. T. Lin, “Improvement of thin palladium silicde films by incorporating phosphorus dopant”, Proceeding of Mater. Res. Symp. Fall Meeting, Boston, U.S.A., 2000 (acceptation for publication in 2001).
  [11]   1. M. H. Juang, C. C. Hwang, and H. C. Cheng, “Effect of RTA on TiN Films as the barrier layer for Pt/BST/Pt capacitors prepared by RF magnetron co-sputter technique at low substrate temperature”, Mater. Res. Symp., Spring Meeting, , San Francisco, U.S.A., 2001.

計畫名稱 計畫總額 執行始於 執行結束 委託單位
以矽為基材之太陽電池結構之研究 573,000 9608 9707 國科會
應用於極低溫製程之微晶矽薄膜電晶體之設計及製作 885,000 0000-00-00 0000-00-00 國科會

指導學生
學年 論文題目 學生
92 矽金氧半場效電晶體於深次微米與功率積體電路應用之設計 歐陽昌義
學年 論文題目 學生
100 大角度離子佈植之薄膜電晶體汲極區域之研究 陳彥名
100 CRLH雙頻帶壓控振盪器與使用變壓器新型壓控振盪器之研製 劉又維
100 採用雙路徑電容放大技術之降壓轉換器 徐稚堯
100 具次閘極結構之橫向式功率金氧半場效電晶體之研究 郭庭佑
99 0.3V之壓控振盪器與高效能四相位壓控振盪器之研究 陳孟信
99 一百奈米穿透式場效電晶體之設計 黃士源
99 穿隧型場效多晶矽薄膜電晶體之研究 劉秉融
99 錳酸鍶鑭陶瓷薄膜應用於微溫度感測元件之研究 王瑞鈞
99 具串聯之空乏型多晶矽薄膜電晶體之複合絕緣閘極雙極性電晶體 謝奇儒
98 溝渠式金氧半蕭特基整流器之特性研究 于鑫龍
98 0.18 μm CMOS 製程之低電壓壓控震盪器之研製 廖英翔
98 新型四相位壓控振盪器與注入鎖定除頻器之設計 陳漢昇
98 CMOS電壓控制振盪器與SiGe注入鎖定除頻器之研製 王承慈
97 陷阱分佈對矽太陽電池特性影響之研究 劉哲孝
97 使用MEMS電感之壓控振盪器及注入鎖定除頻器之設計 溫俊彥
97 多晶矽光二極體與光電晶體之研究 張明全
97 複晶矽薄膜電晶體之結構設計 張家偉
96 光電晶體元件結構設計之研究 陳哲豪
96 新式四相位壓控振盪器及注入鎖定除頻器之設計 黃世新
96 注入鎖定除頻器及壓控震盪器之設計與實作 吳俊毅
96 新型多模注入鎖定除頻器與串疊型電壓控制振盪器之設計 楊昌昊
96 注入鎖定除頻器之設計與實作 林啟文
95 穿透式場效電晶體之研究 胡倍慎
95 異質結構複晶矽/碳化矽薄膜電晶體設計之研究 蔡易伸
94 含矽太陽電池之研究 黃厚穎
94 掩埋層通道複晶矽薄膜電晶體 吳旻霖
93 薄膜電晶體 通道工程之研究 鄭士豪
93 次零點一微米金氧半場效電晶體之元件設計 楊智翔
93 薄膜電晶體汲極工程之研究 邱義銘
93 矽奈米線元件之製作 李東林
92 應用於奈米元件技術之可調功函數閘極於高介電常數介電質上之研究 林天宇
92 高效能溝渠式閘極功率金氧半場效應電晶體之設計 黎志建
91 矽鍺化合物通道之溝渠式閘極功率金氧半場效應電晶體之最佳化設計 闕煒宸
學年 專題題目 學生
93 矽太陽電池之模擬設計 林根鼎
91 異質接面電晶體之特性研究 吳旻霖
89 橫向絕緣閘雙極電晶體(LIGBT)之設計與模擬摘要 陳晉鴻
年份 事蹟