教師資料

鍾勇輝 Yung-Hui Chung
職稱
副教授
學歷
國立交通大學電子博士
電子郵件
yhchung@mail.ntust.edu.tw
辦公室
EE 601-2

Office Hours Wednesday, 09:00~12:00
電話 886-2-27376394
傳真 886-2-27376424
個人網頁 http://homepage.ntust.edu.tw/YHCHUNG/
實驗室 混合訊號IC實驗室 (EE601-2)
研究領域 類比/混合訊號積體電路設計、類比/數位轉換電路(ADC/DAC)、數位校正(Digital Calibration)電路、生醫感測電路(IA)與系統、鎖相迴路
開授課程 資料轉換積體電路、類比IC設計概論、類比IC設計實習、積體電路佈局原理與實習

2017.08 ~  Now 國立台灣科技大學 電子工程系 副教授
2012.09 ~  2017.07 國立台灣科技大學 電子工程系 助理教授
2010.07 ~  2012.08 聯發科技 技術副理
2000.10 ~  2003.10 智原科技 技術經理
1999.05 ~  2000.07 創意電子 資深工程師
1998.03 ~  1999.05 工研院電子所 副工程師
1994.10 ~  1998.03 工研院光電所 副工程師


1994 斐陶斐學會榮譽會員

研究成果
  [1]   Yung-Hui Chung*, Qi-Feng Zeng, and Yi-Shen Lin, “A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme,” accepted by IEEE Trans. Circuits Syst. I, Reg. Papers.
  [2]   Yung-Hui Chung* and Ya-Mien Hsu, "A 12-bit 100-MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme" accepted by IEEE Trans. Circuits Syst. II, Exp. Briefs.
  [3]   Yung-Hui Chung*, Chia-Wei Yen, Pei-Kang Tsai, and Bo-Wei Chen, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme,” IEEE Trans. on VLSI Systems, vol. 26, no. 10, pp. 1989-1998, Oct. 2018.
  [4]   Yung-Hui Chung*, Wei-Shu Rih, and Che-Wei Chang, "A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 8, pp.999-1003, Aug. 2018.
  [5]   Yung-Hui Chung*, Chia-Wei Yen, and Pei-Kang Tsai, "A 12-bit 10-MS/s SAR ADC with a Binary-Window DAC Switching Scheme in 180-nm CMOS," International Journal of Circuit Theory and Applications, vol. 46, no. 4, pp. 748-763, Apr. 2018. https://doi.org/10.1002/cta.2424
  [6]   Yung-Hui Chung* and Chia-Wei Yen, "An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS," IEEE Trans. on VLSI Systems, vol. 25, no. 12, pp. 3434-3443, Dec. 2017.
  [7]   Yung-Hui Chung*, Cheng-Hsun Tsai, and Hsuan-Chih Yeh, "A 5-bit 1-GS/s Binary-Search ADC in 90-nm CMOS," Microelectronics Journal, vol. 63, pp.131-137, Apr. 2017
  [8]   Yung-Hui Chung*, Chia-Wei Yen, and Meng-Hsuan Wu, "A 24-uW 12-b 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS," IEEE Trans. on VLSI Systems, vol. 24, no. 11, pp. 3334-3344, Nov. 2016.
  [9]   Yung-Hui Chung* and Jieh-Tsorng Wu, “A 16-mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” IEEE Trans. on VLSI Systems, vol. 23, no. 3, pp. 557-566, Mar. 2015.
  [10]   Yung-Hui Chung*, Meng-Hsuan Wu and Hung-Sung Li, "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," IEEE Trans. on Circuits and Systems I, vol. 62, no. 1, pp.10-18, Jan. 2015.
  [11]   Yung-Hui Chung* and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2217–2226, Nov., 2010.
  [1]   Yung-Hui Chung and Min-Sheng Chiang, "A 12-bit Synchronous-SAR ADC for IoT Applications," to appear in IEEE ISCAS 2019.
  [2]   Yung-Hui Chung, Chia-Yi Hu, and Che-We Chang, “A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2018, pp. 243–246.
  [3]   Yung-Hui Chung, Hung-Po Ni, Yi-Shen Lin, and Qi-Feng Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018, pp.34-37.
  [4]   Yung-Hui Chung, Hsuan-Chih Yeh, and Che-Wei Chang, 'A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS,' in Proc. of IEEE International Symposium on Next Generation Electronics (ISNE), May 2018, pp.1-2.
  [5]   Yung-Hui Chung and Wei-Shu Rih, “A 6-bit 1.6-GS/s Domino-SAR ADC in 55nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 216-217.
  [6]   Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih, “A 12-bit 160-MS/s Ping-Pong Subranged-SAR ADC in 65nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 5-6. (Best Paper Award)
  [7]   Yung-Hui Chung and Hua-Wei Tseng, “A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS,” in Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Oct. 2017, pp. 1-2.
  [8]   Yung-Hui Chung and Song-Yo Shih, “A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2017, pp. 1-4.
  [9]   Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s Binary-Search ADC in 90nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, pp.334-337.
  [10]   Yung-Hui Chung and Chia-Wei Yen, "A PVT-Tracking Metastability Detector for Asynchronous ADCs," in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2016, pp.1462-1465.
  [11]   Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS," in Proc. IEEE SOC Conference, pp. 25-29, Sep. 2015.
  [12]   Yung-Hui Chung, “Perturbation-Based Digital Background Calibration Technique for Pipelined ADCs,” in Proc. of IEEE Int. Sym. on Circuits and Systems (ISCAS), 2014.
  [13]   Yung-Hui Chung, Meng-Hsuan Wu, and Hung-Sung Li, “A 24uW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2013.
  [14]   Yung-Hui Chung, “The Swapping Binary-Window DAC Switching Technique for SAR ADCs,” in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2013, pp.2231-2234.
  [15]   Meng-Hsuan Wu, Yung-Hui Chung and Hung-Sung Li, “A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2012, pp. 157-160.
  [16]   Yung-Hui Chung and Jieh-Tsorng Wu, “A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” in VLSI Circuits Symp. Dig., Jun. 2011, pp. 128–129.
  [17]   Yung-Hui Chung and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2009, pp. 137–140.
  [1]   Yung-Hui Chung and Bo-Wei Chen, "Successive approximation register analog-to-digital converter and method for operating the same," US Patent 10,211,847
  [2]   Yung-Hui Chung and Bo-Wei Chen, "Signal comparison apparatus and method of controlling same," US Patent 9,395,746
  [3]   Yung-Hui Chung, "METHOD AND APPARATUS FOR PERFORMING NONLINEARITY CALIBRATION," US Patent 8,525,711
  [4]   Meng-Hsuan Wu and Yung-Hui Chung,"SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF," US Patent 8,508,400
  [5]   Yung-Hui Chung and Meng-Hsuan Wu, "Successive approximation register analog-digital converter and method for operating the same," US Patent 8,599,059
  [1]   Yung-Hui Chung, Chia-Wei Yen, and Cheng-Hsun Tsai, "A 12-bit 1-MS/s 26-uW SAR ADC for Sensor Applications," in Nano Devices and Sensors, pp.137-162, 2016, De Gruyter.

計畫名稱 計畫總額 執行始於 執行結束 委託單位
適用超高解析度SAR ADC之數位校正技術分析與設計 新台幣700,000元整 10801 10812 工研院資通所
Calibration Techniques in a 16-bit SAR ADC 新台幣700,000元整 10701 10712 工研院資通所
應用於次世代超音波與通訊系統之十四位元高速類比數位轉換器 新台幣2,544,000元整 10608 10907 科技部
16 bit 1 MS/s SAR ADC 新台幣900,000元整 10601 10612 工研院資通所
高速/高解析度ADC核心電路研究 新台幣700,000元整 10501 10512 工研院資通所
高速高解析ADC核心技術研究 新台幣700,000元整 10401 10412 工研院資通所
應用於高階量測儀器之類比數位轉換器 新台幣 2,379,000元整 10308 10612 國科會
應用於超音波前端電路之12-bit 100-MS/s ADC 新台幣700,000元整 10305 10312 工研院資通所
高速/高解析度ADC核心電路研究 新台幣700,000元整 10201 10212 工研院資通所
高效能十二位元漸進式類比數位轉換器電路設計 新台幣1,800,000元整 10111 10307 國科會

指導學生
學年 論文題目 學生
學年 論文題目 學生
107 Low Jitter PLL Design Techniques 馬世為
107 A 14b 1-GS/s TI Calibration ADC 邱慶秦
107 Noise-Shaping SAR ADC 林仕祥
107 A 10b 5GS/s TI-SAR ADC 吳道展
106 A 16b Calibration SAR ADC 曾啟峰
106 Low-Jitter Multi-Phase Clock Generation Circuit 黃弘鈞
105 Design and Implementation of 12-bit SAR ADCs for Biomedical and IoT Applications 江民陞
105 Design and Implementation of 14-bit Pipeline-SAR ADCs with a Background Nonlinearity Calibration Scheme (旺宏電子) 林益申
105 Design and Implementation of 10-bit 2b/cycle-Assisted SAR ADCs (盛群半導體) 賴軍維
104 一個十六位元每秒一百萬次取樣之免校正連續漸進式類比數位轉換器設計與實現 (已畢業,智原科技) 田佳輝
104 十二位元次階連續漸進式類比數位轉換器之設計與實現 (已畢業,工研院資通所) 日韋舒
104 八位元超高速連續漸進式類比數位轉換器之設計與實現 (已畢業,義隆電子) 張哲瑋
103 使用單次二位元運算於十位元高速漸進式類比數位轉換器之設計與實現 (已畢業,敦泰電子) 曾華偉
103 用於高速時間交錯類比數位轉換器之時脈校正處理器設計 (已畢業, 瑞昱半導體) 胡嘉翊
103 A 12-bit 100-MS/s SAR ADC (已畢業, 晶豪科技) 許雅綿
103 使用非線性背景校正技術之十四位元類比數位轉換器 (已畢業,揚智科技) 李念祖
103 使用二元視窗切換技術之十二位元漸進式類比數位轉換器 (已畢業) 倪宏博
102 An 8-bit 1.25-GS/s ADC (已畢業,敦泰電子) 蔡政勳
102 A 12-bit 100-MS/s SAR ADC (已畢業) 顏嘉威
102 A 12-bit 100-MS/s ADC (已畢業,工研院資通所) 施松佑
102 A 10-bit 160-MS/s ADC (已畢業, UMC) 葉烜志
學年 專題題目 學生
108 A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time 陳品豪、吳昇翰
108 Capacitorless Self-Clocked All-Digital Low-Dropout Regulator 余心豪、賴冠衡
108 Switched Capacitor based High Positive and Negative Voltage Charge-pump 林賢順、蔡旻修、何宗翰
107 Bandgap Reference Circuits: Group-2 謝昱廷,莊懿
107 Bandgap Reference Circuits: Group-1 林惟鍾,林巨彥
107 Analog and digital circuit implementation 王挺安、蕭靖燁
106 Bandgap Reference and Regulators 周郁桀、邵丞擇、馬世為
105 A 10-bit 100-KS/s SAR ADC 賴冠亨、李榮章
105 A biomedical analog front-end (AFE) circuit: IA + PGA 邱宥榮、游景賀
105 A LDO regulator for biomedical AFE circuits 曾俊銘、江振忠
105 A bandgap circuit design 葉建祖
105 An analog front-end (receiver) circuits for logic analyzers (LAs) 洪宇廷
104 A 10-bit 100-MS/s SAR ADC 池振聖、侯人文
104 A 10-bit 1-MS/s SAR ADC 胡家瑋、朱致緯
104 Bandgap Reference Circuits 簡國訓、黃林育麟
104 ADC and IA Testing 林道、黃金增
103 能量採集系統設計 黃揚景、林鈺翔
103 生醫感測系統設計 唐煜杰、劉建宏
103 高速儀表類比前端電路設計 鄧逸祥
102 生醫前端積體電路設計 洪瑋謙, 張振誠
102 十二位元數位類比轉換器電路設計 楊政穎
101 生醫感測系統設計 孫以諾,謝曜竹,任欣圻
年份 事蹟