鍾勇輝 Yung-Hui Chung

職稱
鍾勇輝 Yung-Hui Chung
教授
學歷
國立交通大學電子博士
電子郵件
yhchung@mail.ntust.edu.tw
辦公室
EE 601-2

Office Hours	Wednesday, 10:00~12:00
電話	886-2-27376394
個人網頁	https://sites.google.com/view/ntust-yhchung
實驗室	混合訊號IC實驗室 (EE601-2)
研究領域	類比/混合訊號積體電路設計、類比/數位轉換電路(ADC/DAC)、數位校正(Digital Calibration)電路、生醫感測電路(IA)
開授課程	類比積體電路專論、資料轉換積體電路、類比IC設計概論、類比IC設計與應用、積體電路佈局原理與實習

現職及經歷

2023.02 ~ 迄今	國立台灣科技大學電子工程系教授
2017.08 ~ 2023.01	國立台灣科技大學電子工程系副教授
2012.09 ~ 2017.07	國立台灣科技大學電子工程系助理教授
2010.07 ~ 2012.08	聯發科技技術副理
2000.10 ~ 2003.10	智原科技技術經理
1999.05 ~ 2000.07	創意電子資深工程師
1998.03 ~ 1999.05	工研院電子所副工程師
1994.10 ~ 1998.03	工研院光電所副工程師

重要研究成果

[1]	Research Topics (English)
[2]	研究主題 (中文)

榮譽及獎勵

1994

斐陶斐學會榮譽會員

研究成果

期刊論文

[1]	Yung-Hui Chung*, Chia-Hui Tien, and Qi-Feng Zeng, “A 16-bit Calibration-Free SAR ADC with Binary-Window and Capacitor-Swapping DAC Switching Schemes,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 69, no. 1, pp. 88–99, Jan. 2022
[2]	Yung-Hui Chung* and Wei-Shu Rih, “A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs. vol. 67, no. 4, pp. 645–649, Apr. 2020.
[3]	Yung-Hui Chung*, Qi-Feng Zeng, and Yi-Shen Lin, “A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 2, pp. 358–368, Feb. 2020.
[4]	Yung-Hui Chung* and Ya-Mien Hsu, "A 12-bit 100-MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 7, pp. 1094-1098, Jul. 2019.
[5]	Yung-Hui Chung*, Chia-Wei Yen, Pei-Kang Tsai, and Bo-Wei Chen, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme,” IEEE Trans. on VLSI Systems, vol. 26, no. 10, pp. 1989-1998, Oct. 2018.
[6]	Yung-Hui Chung*, Wei-Shu Rih, and Che-Wei Chang, "A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 8, pp.999-1003, Aug. 2018.
[7]	Yung-Hui Chung*, Chia-Wei Yen, and Pei-Kang Tsai, "A 12-bit 10-MS/s SAR ADC with a Binary-Window DAC Switching Scheme in 180-nm CMOS," International Journal of Circuit Theory and Applications, vol. 46, no. 4, pp. 748-763, Apr. 2018. https://doi.org/10.1002/cta.2424
[8]	Yung-Hui Chung* and Chia-Wei Yen, "An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS," IEEE Trans. on VLSI Systems, vol. 25, no. 12, pp. 3434-3443, Dec. 2017.
[9]	Yung-Hui Chung*, Cheng-Hsun Tsai, and Hsuan-Chih Yeh, "A 5-bit 1-GS/s Binary-Search ADC in 90-nm CMOS," Microelectronics Journal, vol. 63, pp.131-137, Apr. 2017
[10]	Yung-Hui Chung*, Chia-Wei Yen, and Meng-Hsuan Wu, "A 24-uW 12-b 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS," IEEE Trans. on VLSI Systems, vol. 24, no. 11, pp. 3334-3344, Nov. 2016.
[11]	Yung-Hui Chung* and Jieh-Tsorng Wu, “A 16-mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” IEEE Trans. on VLSI Systems, vol. 23, no. 3, pp. 557-566, Mar. 2015.
[12]	Yung-Hui Chung*, Meng-Hsuan Wu and Hung-Sung Li, "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," IEEE Trans. on Circuits and Systems I, vol. 62, no. 1, pp.10-18, Jan. 2015.
[13]	Yung-Hui Chung* and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2217–2226, Nov., 2010.

會議論文

[1]	Zi-Chi Lin, Chun-Yang Chiu, and Yung-Hui Chung, “A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOS,” to appear in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2024.
[2]	Yung-Hui Chung and Jyun-Hau Kuo, “A 12b Dual-Mode SAR ADC for Bio-Medical Applications,” accepted by IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2024.
[3]	Qi-Fen Zeng, Chia-Hui Tien, and Yung-Hui Chung, “A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme,” IEEE Int. Sym. on Circuits and Systems (ISCAS), May 2024, pp. 1-4.
[4]	Wei-Chung Lin, Yung-Chi Chang, and Yung-Hui Chung*, “A 10b 400MS/s 2x-Time-Interleaved 2-Then- 1b/Cycle SAR ADC in 90nm CMOS,” IEEE Int. Sym. on Circuits and Systems (ISCAS), May 2024, pp. 1-5.
[5]	Hou-Hsuan Lin, Jia-Fong Shih, and Yung-Hui Chung, ”A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Applications,” in Proc. of International SoC Design Conference (ISOCC), Oct. 2023.
[6]	Yung-Hui Chung, Chia-Hui Tien, and Qi-Feng Zeng, “A 16-bit Calibration-Free SAR ADC with Binary-Window and Capacitor-Swapping DAC Switching Schemes,” accepted by IEEE ISICAS 2021
[7]	Yung-Hui Chung, Jia-Fong Shih and Yu-Hsiang Wang, "A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation," accepted by IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2021
[8]	Bo-Wei Chen, Yung-Hui Chung, and Chia-Ming Tsai, "An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique," accepted by IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), 2021.
[9]	Yung-Hui Chung and Qi-Feng Zeng, “A 12-bit 100-kS/s SAR ADC for IoT Applications,” IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Aug. 2020, pp. 1-4.
[10]	Yung-Hui Chung, Qi-Feng Zeng, and Chia-Hui Tien, “A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 5-8.
[11]	Yung-Hui Chung, “A 12-bit Domino ADC with a Background Offset Calibration Scheme,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 9-12
[12]	Yung-Hui Chung and Min-Sheng Chiang, "A 12-bit Synchronous-SAR ADC for IoT Applications," IEEE Int. Sym. on Circuits and Systems (ISCAS), May 2019, pp. 1-5.
[13]	Yung-Hui Chung, Chia-Yi Hu, and Che-We Chang, “A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2018, pp. 243–246.
[14]	Yung-Hui Chung, Hung-Po Ni, Yi-Shen Lin, and Qi-Feng Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018, pp.34-37.
[15]	Yung-Hui Chung, Hsuan-Chih Yeh, and Che-Wei Chang, 'A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS,' in Proc. of IEEE International Symposium on Next Generation Electronics (ISNE), May 2018, pp.1-2.
[16]	Yung-Hui Chung and Wei-Shu Rih, “A 6-bit 1.6-GS/s Domino-SAR ADC in 55nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 216-217.
[17]	Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih, “A 12-bit 160-MS/s Ping-Pong Subranged-SAR ADC in 65nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 5-6. (Best Paper Award)
[18]	Yung-Hui Chung and Hua-Wei Tseng, “A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS,” in Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Oct. 2017, pp. 1-2.
[19]	Yung-Hui Chung and Song-Yo Shih, “A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2017, pp. 1-4.
[20]	Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s Binary-Search ADC in 90nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, pp.334-337.
[21]	Yung-Hui Chung and Chia-Wei Yen, "A PVT-Tracking Metastability Detector for Asynchronous ADCs," in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2016, pp.1462-1465.
[22]	Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS," in Proc. IEEE SOC Conference, pp. 25-29, Sep. 2015.
[23]	Yung-Hui Chung, “Perturbation-Based Digital Background Calibration Technique for Pipelined ADCs,” in Proc. of IEEE Int. Sym. on Circuits and Systems (ISCAS), 2014.
[24]	Yung-Hui Chung, Meng-Hsuan Wu, and Hung-Sung Li, “A 24uW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2013.
[25]	Yung-Hui Chung, “The Swapping Binary-Window DAC Switching Technique for SAR ADCs,” in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2013, pp.2231-2234.
[26]	Meng-Hsuan Wu, Yung-Hui Chung and Hung-Sung Li, “A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2012, pp. 157-160.
[27]	Yung-Hui Chung and Jieh-Tsorng Wu, “A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” in VLSI Circuits Symp. Dig., Jun. 2011, pp. 128–129.
[28]	Yung-Hui Chung and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2009, pp. 137–140.

專利

[1]	Yung-Hui Chung and Bo-Wei Chen, "Successive approximation register analog-to-digital converter and method for operating the same," US Patent 10,211,847
[2]	Yung-Hui Chung and Bo-Wei Chen, "Signal comparison apparatus and method of controlling same," US Patent 9,395,746
[3]	Yung-Hui Chung, "METHOD AND APPARATUS FOR PERFORMING NONLINEARITY CALIBRATION," US Patent 8,525,711
[4]	Meng-Hsuan Wu and Yung-Hui Chung,"SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF," US Patent 8,508,400
[5]	Yung-Hui Chung and Meng-Hsuan Wu, "Successive approximation register analog-digital converter and method for operating the same," US Patent 8,599,059

著作

[1]	Yung-Hui Chung, Chia-Wei Yen, and Cheng-Hsun Tsai, "A 12-bit 1-MS/s 26-uW SAR ADC for Sensor Applications," in Nano Devices and Sensors, pp.137-162, 2016, De Gruyter.

其他

研究成果

研究計畫

計畫名稱	計畫總額	執行始於	執行結束	委託單位
A 16b SAR ADC IP design and implementation	新台幣1,000,000元整	11311	11410	普誠科技
12bit 800Mbps Time-Interleaving SAR ADC	新台幣500,000元整	11310	11409	智原科技
超高解析度數位類比轉換器之研究與晶片實現	新台幣3,804,000元整	11308	11607	國科會
A 7b 56GS/s TI ADC IP design and implementation	新台幣1,200,000元整	11304	11406	獵速科技
A 16b ADC IP design and implementation in TSMC 90nm CMOS	新台幣1,200,000元整	11301	11406	蘭芯系統
Delta-Sigma Modulator 晶片設計與實現	新台幣500,000元整	11210	11309	矽創電子
高精度數位類比轉換器之電路實現與專利開發	新台幣600,000元整	11201	11212	工研院電光所
Advanced SAR ADC	新台幣300,000元整	11109	11208	蘭芯系統
高解析度低功耗SAR ADC設計	新台幣500,000元整	1117	1126	矽創電子
高階精準類比數位轉換器與數位類比轉換器之晶片實現	新台幣1,100,000元整	1111	11112	工研院電光所
次世代超高解析度類比數位轉換器之研究與晶片驗證 (三年期)	新台幣3,540,000元整	11008	11307	科技部
Research and Development of 16-bit SAR ADCs	新台幣1,000,000元整	11003	11112	江左盟科技有限公司
高階精準感測資料轉換電路之研究開發與晶片實現	新台幣1,200,000元整	11001	11012	工研院資通所
28nm ADC 設計開發研究	新台幣432,000元整	10909	11008	聯華電子
超高解析度類比數位轉換器之研究與晶片實現	新台幣941,000元整	10908	11007	科技部
超高解析度逐次漸進式類比數位轉換器之架構分析與模型建立	新台幣500,000元整	10904	10912	工研院資通所
適用超高解析度SAR ADC之數位校正技術分析與設計	新台幣700,000元整	10801	10812	工研院資通所
Calibration Techniques in a 16-bit SAR ADC	新台幣700,000元整	10701	10712	工研院資通所
應用於次世代超音波與通訊系統之十四位元高速類比數位轉換器 (三年期)	新台幣2,544,000元整	10608	10907	科技部
16 bit 1 MS/s SAR ADC	新台幣900,000元整	10601	10612	工研院資通所
高速/高解析度ADC核心電路研究	新台幣700,000元整	10501	10512	工研院資通所
高速高解析ADC核心技術研究	新台幣700,000元整	10401	10412	工研院資通所
應用於高階量測儀器之類比數位轉換器 (三年期)	新台幣 2,379,000元整	10308	10612	國科會
應用於超音波前端電路之12-bit 100-MS/s ADC	新台幣700,000元整	10305	10312	工研院資通所
高速/高解析度ADC核心電路研究	新台幣700,000元整	10201	10212	工研院資通所
高效能十二位元漸進式類比數位轉換器電路設計 (二年期)	新台幣1,800,000元整	10111	10307	國科會

指導學生

博士生

學年	論文題目	學生

碩士生

學年	論文題目	學生
110	一個二階雜訊整形連續漸進式類比數位轉換器與前景式電容校正技術之設計與實現 (畢業 => 瑞昱半導體)	施佳鳳
110	基於浮動反向式放大器的離散型三角積分類比數位轉換器之設計與實現 (畢業 => 瑞昱半導體)	江雅茹
110	基於環形放大器與相關性電壓位準移位技術之管線式類比數位轉換器設計與實現 (畢業 => 瑞昱半導體)	吳俊緯
110	低功耗及超高解析度之電容校正逐次漸進式類比數位轉換器設計 (畢業 => 瑞昱半導體)	張凱棋
110	一個使用數位非線性校正技術的十四位元管線漸進式類比數位轉換器 (畢業 => )	柯泳譯
110	一個十位元每秒三十二億次取樣之四通道時間交錯管線式連續漸進類比數位轉換器 (畢業 => )	張詠淇
110	十位元高速數位至類比轉換器之設計與晶片實現 (畢業 => 瑞昱半導體)	林芯聿
109	一個使用殘值超取樣及二元視窗之十六位元逐次漸進式類比數位轉換器之設計與實現 (畢業 => 原相科技)	張廷綱
109	採用前景電容校正技術之十六位元逐次漸進式類比數位轉換器設計與實現 (畢業 => 瑞昱半導體)	陳品豪
109	雜訊整形連續漸進式類比數位轉換器與電容不匹配削減技術之設計與實現 (畢業 => 瑞昱半導體)	高培修
109	一個二十位元前景式校正之電阻式數位類比轉換器 (畢業 => 奇景光電)	曾允珩
109	一個音頻應用的離散型動態縮放類比數位轉換器之設計與實現 (畢業 => 瑞昱半導體)	林子圻
109	使用被動電荷傳輸的十位元每秒五億次取樣乒乓型管線化連續漸進式類比數位轉換器 (畢業 => 新唐科技)	何瑞雯
108	十位元超高速類比數位轉換器在二十八奈米互補金氧半導體製程之設計與實現 (已畢業，揚智科技)	周庭緯
108	一個使用電容校正技術的混合式二十位元逐次漸進式類比數位轉換器之設計與實現 (已畢業，原相科技)	于厚澤
108	Discrete-Time Dynamic Zoom ADC for Audio Applications (已畢業，瑞昱半導體)	周棋緯
108	An 8-bit TI ADC for High-Speed Serial Link Receivers (已畢業，嘉雨思科技)	莊懿
108	A 14-bit 250MS/s 2-Way Time-Interleaved ADC with a Background Calibration Scheme (已畢業，瑞昱半導體)	林惟鍾
108	A Discrete-Time Audio Delta-Sigma Modulator (已畢業，瑞昱半導體)	林后軒
107	Low Jitter PLL Design Techniques (已畢業，)	馬世為
107	使用背景式非線性校正技術的十四位元二階式類比數位轉換器之設計與實現 (已畢業，達發科技)	邱慶秦
107	使用有限脈衝濾波器架構之雜訊整形連續漸進式類比至數位轉換器設計 (已畢業，揚智科技)	林仕祥
107	十位元高速連續漸進式類比數位轉換器之設計與實現 (已畢業，盛群半導體)	吳道展
106	一個使用電容校正技術的十六位元逐次漸進式類比數位轉換器之設計與實現 (已畢業，瑞昱半導體)	曾啟峰
106	低抖動鎖相迴路之電路設計與實現 (已畢業，鈺創科技)	黃弘鈞
105	十二位元極低功率連續漸進式類比數位轉換器之設計與實現 (已畢業，天鈺科技)	江民陞
105	使用非線性背景校正之十四位元管線連續逼近式類比數位轉換器設計與實現 (已畢業，創意電子)	林益申
105	使用單次二位元輔助之十位元漸進式類比數位轉換器設計與實現 (已畢業，盛群半導體)	賴軍維
104	一個十六位元每秒一百萬次取樣之免校正連續漸進式類比數位轉換器設計與實現 (已畢業，智原科技)	田佳輝
104	十二位元次階連續漸進式類比數位轉換器之設計與實現 (已畢業，工研院資通所)	日韋舒
104	八位元超高速連續漸進式類比數位轉換器之設計與實現 (已畢業，義隆電子)	張哲瑋
103	使用單次二位元運算於十位元高速漸進式類比數位轉換器之設計與實現 (已畢業，敦泰電子)	曾華偉
103	用於高速時間交錯類比數位轉換器之時脈校正處理器設計 (已畢業, 瑞昱半導體)	胡嘉翊
103	一個使用二元視窗切換技術之十二位元每秒一億次取樣次階-連續漸進式類比至數位轉換器 (已畢業, 晶豪科技)	許雅綿
103	使用非線性背景校正技術之十四位元類比數位轉換器 (已畢業，揚智科技)	李念祖
103	使用二元視窗切換技術之十二位元漸進式類比數位轉換器 (已畢業)	倪宏博
102	一個八位元每秒十二億五千萬次取樣之次階-連續漸進式類比至數位轉換器設計與實現 (已畢業，敦泰電子)	蔡政勳
102	每秒一億次取樣之十二位元連續漸進式類比數位轉換器設計與實現 (已畢業，智原科技)	顏嘉威
102	使用電容交換技術之低功耗逐次逼近式類比數位轉換器設計 (已畢業，工研院資通所)	施松佑
102	每秒一億六千萬次取樣之十位元連續漸進式類比數位轉換器設計與實現 (已畢業, UMC)	葉烜志

指導專題

學年	專題題目	學生
113	A 13-bit 1-MS/s SAR ADC	莊凱喬、張閔華、高子惟
113	A 10-bit 20-MS/s SAR ADC	張雅欣、張鈺敏、鄭名佑
112	A 10-bit 20-MS/s SAR ADC	蔡柏賢、黃于賢、江豐毅
112	A 13-bit 1-MS/s SAR ADC	李育維、朱啟元、楊振弘
111	An 11-nW CMOS Temperature-to-Digital Converter	馬浩鈞、歐陽晁祐
111	A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference	吳佳翰、邱雋洋
111	A 1-mW Class-AB Amplifier for High-Fidelity 16 Ω Headphones	彭浚祐、江梓維
111	A 192-pW Voltage Reference	邱壬鋐、郭哲原
110	生醫前端類比電路	王昱晴、劉晴華
110	溫度感測與轉換電路	簡瑞智、張上為
110	CMOS Bandgap Voltage Reference	游心慈
109	A 150 nW CMOS Temperature Sensor	侯宏諭、張聖群
109	An 11-nW CMOS Temperature-to-Digital Converter	江雅茹、紀宏憲
109	A Fully-Integrated 71 nW CMOS Temperature Sensor	倪隆靖、呂永玄
109	A Class-AB Amplifier With −101 dB THD+N	陳冠余、蕭瑜葶
109	A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference	王昱翔、施佳鳳
108	A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time	陳品豪、吳昇翰
108	Capacitorless Self-Clocked All-Digital Low-Dropout Regulator	余心豪、賴冠衡
108	Switched Capacitor based High Positive and Negative Voltage Charge-pump	林賢順、蔡旻修、何宗翰
107	Bandgap Reference Circuits: Group-2	謝昱廷，莊懿
107	Bandgap Reference Circuits: Group-1	林惟鍾，林巨彥
107	Analog and digital circuit implementation	王挺安、蕭靖燁
106	Bandgap Reference and Regulators	周郁桀、邵丞擇、馬世為
105	A 10-bit 100-KS/s SAR ADC	賴冠亨、李榮章
105	A biomedical analog front-end (AFE) circuit: IA + PGA	邱宥榮、游景賀
105	A LDO regulator for biomedical AFE circuits	曾俊銘、江振忠
105	A bandgap circuit design	葉建祖
105	An analog front-end (receiver) circuits for logic analyzers (LAs)	洪宇廷
104	A 10-bit 100-MS/s SAR ADC	池振聖、侯人文
104	A 10-bit 1-MS/s SAR ADC	胡家瑋、朱致緯
104	Bandgap Reference Circuits	簡國訓、黃林育麟
104	ADC and IA Testing	林道、黃金增
103	能量採集系統設計	黃揚景、林鈺翔
103	生醫感測系統設計	唐煜杰、劉建宏
103	高速儀表類比前端電路設計	鄧逸祥
102	生醫前端積體電路設計	洪瑋謙, 張振誠
102	十二位元數位類比轉換器電路設計	楊政穎
101	生醫感測系統設計	孫以諾，謝曜竹，任欣圻

特殊榮譽

年份	事蹟
2024	113學年度電子系專題競賽優勝 (學生: 莊凱喬、高子惟、張閔華)
2022	奇景盃IC佈局競賽佳作 (學生: 莊懿)
2021	110學年度電子系專題競賽優勝 (學生:簡瑞智、張上為)
2020	109學年度電子系專題競賽優勝 (學生: 王昱翔、施佳鳳)
2019	奇景盃IC佈局競賽佳作 (學生: 周棋緯、謝昱廷)
2019	108學年度電子系專題競賽優勝 (學生: 余心豪、郭建鋒)
2018	107學年度電子系專題競賽優勝 (學生: 林惟鍾、莊懿)
2017	ISOCC 2017, Best Paper Award (Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih)