Faculty

鍾勇輝 Yung-Hui Chung photo
Position
Associate Professor
Education
PhD., Electronics Engineering, National Chiao-Tung University
E-mail
yhchung@mail.ntust.edu.tw
Room
EE 601-2

Office Hours Wednesday, 09:00~12:00
Telephone 886-2-27376394
FAX 886-2-27376424
Homepage http://homepage.ntust.edu.tw/YHCHUNG/
Laboratory Mixed-Signal IC Laboratory (EE601-2)
Major Field Analog/Mixed-signal IC Design, Data Conversion Circuits, Digital Calibration Circuits, Biomedical Analog Front-End Circuits
Course Advanced Topics on Analog Integrated Circuits, VLSI Data Conversion Circuits, Introduction to Analog Circuit Design, Analog Circuit Design and Applications, Integrated Circuit Layout Practice

2017.08 ~ Now Associate Professor, DECE, NTUST
2012.09 ~ 2017.07 Assistant Professor, DECE, NTUST
2010.07 ~ 2012.08 Technical Manager, MediaTek Inc.
2000.10 ~ 2003.10 Technical Manager, Faraday Tech.
1999.05 ~ 2000.07 Senior Engineer, Global UniChip
1998.03 ~ 1999.05 Engineer, ERSO, ITRI
1994.10 ~ 1998.03 Engineer, OES, ITRI


1994 斐陶斐學會榮譽會員

Research Achievement
  [1]   Yung-Hui Chung* and Wei-Shu Rih, “A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs. vol. 67, no. 4, pp. 645–649, Apr. 2020.
  [2]   Yung-Hui Chung*, Qi-Feng Zeng, and Yi-Shen Lin, “A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 2, pp. 358–368, Feb. 2020.
  [3]   Yung-Hui Chung* and Ya-Mien Hsu, "A 12-bit 100-MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 7, pp. 1094-1098, Jul. 2019.
  [4]   Yung-Hui Chung*, Chia-Wei Yen, Pei-Kang Tsai, and Bo-Wei Chen, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme,” IEEE Trans. on VLSI Systems, vol. 26, no. 10, pp. 1989-1998, Oct. 2018.
  [5]   Yung-Hui Chung*, Wei-Shu Rih, and Che-Wei Chang, "A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 8, pp.999-1003, Aug. 2018.
  [6]   Yung-Hui Chung*, Chia-Wei Yen, and Pei-Kang Tsai, "A 12-bit 10-MS/s SAR ADC with a Binary-Window DAC Switching Scheme in 180-nm CMOS," International Journal of Circuit Theory and Applications, vol. 46, no. 4, pp. 748-763, Apr. 2018. https://doi.org/10.1002/cta.2424
  [7]   Yung-Hui Chung* and Chia-Wei Yen, "An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS," IEEE Trans. on VLSI Systems, vol. 25, no. 12, pp. 3434-3443, Dec. 2017.
  [8]   Yung-Hui Chung*, Cheng-Hsun Tsai, and Hsuan-Chih Yeh, "A 5-bit 1-GS/s Binary-Search ADC in 90-nm CMOS," Microelectronics Journal, vol. 63, pp.131-137, Apr. 2017
  [9]   Yung-Hui Chung*, Chia-Wei Yen, and Meng-Hsuan Wu, "A 24-uW 12-b 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS," IEEE Trans. on VLSI Systems, vol. 24, no. 11, pp. 3334-3344, Nov. 2016.
  [10]   Yung-Hui Chung* and Jieh-Tsorng Wu, “A 16-mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” IEEE Trans. on VLSI Systems, vol. 23, no. 3, pp. 557-566, Mar. 2015.
  [11]   Yung-Hui Chung*, Meng-Hsuan Wu and Hung-Sung Li, "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," IEEE Trans. on Circuits and Systems I, vol. 62, no. 1, pp.10-18, Jan. 2015.
  [12]   Yung-Hui Chung* and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2217–2226, Nov., 2010.
  [1]   Yung-Hui Chung, Chia-Hui Tien, and Qi-Feng Zeng, “A 16-bit Calibration-Free SAR ADC with Binary-Window and Capacitor-Swapping DAC Switching Schemes,” accepted by IEEE ISICAS 2021
  [2]   Yung-Hui Chung, Jia-Fong Shih and Yu-Hsiang Wang, "A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation," accepted by IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2021
  [3]   Bo-Wei Chen, Yung-Hui Chung, and Chia-Ming Tsai, "An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique," accepted by IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), 2021.
  [4]   Yung-Hui Chung and Qi-Feng Zeng, “A 12-bit 100-kS/s SAR ADC for IoT Applications,” IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Aug. 2020, pp. 1-4.
  [5]   Yung-Hui Chung, Qi-Feng Zeng, and Chia-Hui Tien, “A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 5-8.
  [6]   Yung-Hui Chung, “A 12-bit Domino ADC with a Background Offset Calibration Scheme,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 9-12
  [7]   Yung-Hui Chung and Min-Sheng Chiang, "A 12-bit Synchronous-SAR ADC for IoT Applications," IEEE Int. Sym. on Circuits and Systems (ISCAS), May 2019, pp. 1-5.
  [8]   Yung-Hui Chung, Chia-Yi Hu, and Che-We Chang, “A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2018, pp. 243–246.
  [9]   Yung-Hui Chung, Hung-Po Ni, Yi-Shen Lin, and Qi-Feng Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018, pp.34-37.
  [10]   Yung-Hui Chung, Hsuan-Chih Yeh, and Che-Wei Chang, 'A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS,' in Proc. of IEEE International Symposium on Next Generation Electronics (ISNE), May 2018, pp.1-2.
  [11]   Yung-Hui Chung and Wei-Shu Rih, “A 6-bit 1.6-GS/s Domino-SAR ADC in 55nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 216-217.
  [12]   Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih, “A 12-bit 160-MS/s Ping-Pong Subranged-SAR ADC in 65nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 5-6. (Best Paper Award)
  [13]   Yung-Hui Chung* and Hua-Wei Tseng, “A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS,” in Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Oct. 2017, pp. 1-2.
  [14]   Yung-Hui Chung and Song-Yo Shih, “A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2017, pp. 1-4.
  [15]   Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s Binary-Search ADC in 90nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, pp.334-337.
  [16]   Yung-Hui Chung and Chia-Wei Yen, "A PVT-Tracking Metastability Detector for Asynchronous ADCs," in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2016, pp.1462-1465.
  [17]   Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS," in Proc. IEEE SOC Conference, pp. 25-29, Sep. 2015.
  [18]   Yung-Hui Chung, “Perturbation-Based Digital Background Calibration Technique for Pipelined ADCs,” in Proc. of IEEE Int. Sym. on Circuits and Systems (ISCAS), 2014.
  [19]   Yung-Hui Chung, Meng-Hsuan Wu, and Hung-Sung Li, “A 24uW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2013.
  [20]   Yung-Hui Chung, “The Swapping Binary-Window DAC Switching Technique for SAR ADCs,” in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2013, pp.2231-2234.
  [21]   Meng-Hsuan Wu, Yung-Hui Chung and Hung-Sung Li, “A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2012, pp. 157-160.
  [22]   Yung-Hui Chung and Jieh-Tsorng Wu, “A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” in VLSI Circuits Symp. Dig., Jun. 2011, pp. 128–129.
  [23]   Yung-Hui Chung and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2009, pp. 137–140.
  [1]   Yung-Hui Chung and Bo-Wei Chen, "Successive approximation register analog-to-digital converter and method for operating the same," US Patent 10,211,847
  [2]   Yung-Hui Chung and Bo-Wei Chen, "Signal comparison apparatus and method of controlling same," US Patent 9,395,746
  [3]   Yung-Hui Chung, "METHOD AND APPARATUS FOR PERFORMING NONLINEARITY CALIBRATION," US Patent 8,525,711
  [4]   Meng-Hsuan Wu and Yung-Hui Chung,"SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF," US Patent 8,508,400
  [5]   Yung-Hui Chung and Meng-Hsuan Wu, "Successive approximation register analog-digital converter and method for operating the same," US Patent 8,599,059
  [1]   Yung-Hui Chung, Chia-Wei Yen, and Cheng-Hsun Tsai, "A 12-bit 1-MS/s 26-uW SAR ADC for Sensor Applications," in Nano Devices and Sensors, pp.137-162, 2016, De Gruyter.

Research Achievement
Title Total Amount Conduct From Conduct Until Client
Research and chip verification for next-generation ultra-high resolution ADCs 新台幣3,540,000元整 11008 11307 MOST
Research and Development of 16-bit SAR ADCs 新台幣1,000,000元整 11003 11112 Chivalry Technologies Limited
Research and chip implementation of high precision sensing data conversion circuits 新台幣1,200,000元整 11001 11012 ITRI
Research and Development of an ADC in 28nm CMOS 新台幣432,000元整 10909 11008 UMC
Research and Implementation of Ultra-High-Resolution ADCs 新台幣941,000元整 10908 11007 MOST
Modeling and Architecture Analysis of Ultra-High-Resolution SAR ADCs 新台幣500,000元整 10904 10912 CCL/ITRI
Design and Analysis of Digital Calibration Techniques for ultra-high resolution SAR ADCs 新台幣700,000元整 10801 10812 CCL/ITRI
Calibration Techniques in a 16-bit SAR ADC 新台幣700,000元整 10701 10712 CCL/ITRI
14-bit High-Speed ADCs for Next-Generation Ultrasonic and Communication Systems 新台幣2,544,000元整 10608 10907 MOST
16 bit 1 MS/s SAR ADC 新台幣900,000元整 10601 10612 ITRI
Research of a high-speed and high-resolution ADC architecture 新台幣700,000元整 10501 10512 CCL/ITRI
Research of a high-speed and high-resolution ADC architecture 新台幣700,000元整 10401 10412 ITRI
Analog-to-Digital Converters for Advanced Measuring Instruments 新台幣 2,379,000元整 10308 10612 NSC
A 12-bit 100-MS/s ADC for Ultrasound AFE 新台幣700,000元整 10305 10312 ITRI
Research of a high-speed and high-resolution ADC architecture 新台幣700,000元整 10201 10212 ITRI
High-Efficiency 12-bit Successive-Approximation Register Analog-to-Digital Converter Design 新台幣1,800,000元整 10111 10307 NSC

Student
Academic Year Thesis Title Student
M.S
Academic Year Thesis Title Student
109 16b SAR ADCs 張廷綱
109 A 20b Hybrid ADC for Instrumentation Applications 陳品豪
109 Noise-shaping SAR ADCs 高培修
109 A 20-bit DAC with Calibration Scheme 曾允珩
109 A VCO-based CT-DSM ADC 林子圻
109 A 12b Pipelined ADC 何瑞雯
108 A 10-bit 5-GS/s Time-Interleaved ADC 周庭緯
108 A 20-bit Hybrid-SAR ADC 于厚澤
108 A Zoom ADC with over100dB DR 周棋緯
108 An 8-bit TI ADC for High-Speed Serial Link Receivers 莊懿
108 A 14-bit 1-GS/s Time-Interleaved ADC with Background Calibration Schemes 林惟鍾
108 A Discrete-Time Audio Delta-Sigma Modulator 林后軒
107 Low Jitter PLL Design Techniques 馬世為
107 Design and Implementation of 14-bit Two-Step ADCs with a Background Nonlinearity Calibration Scheme 邱慶秦
107 Design of Noise-Shaping SAR ADCs with FIR Filter Structure 林仕祥
107 Design and Implementation of 10-bit High-Speed SAR ADCs 吳道展
106 Design and Implementation of a 16b SAR ADC Using a Capacitor Calibration Scheme (Graduated, RealTek) 曾啟峰
106 Design and Implementation of Low-Jitter Phase-Locked Loops 黃弘鈞
105 Design and Implementation of 12-bit Ultra-Low-Power SAR ADCs Min-Sheng Chiang
105 Design and Implementation of 14-bit Pipeline-SAR ADCs with a Background Nonlinearity Calibration Scheme Eason Lin
105 Design and Implementation of 10-bit 2b/cycle-Assisted SAR ADCs Edward Lai
104 Design and Implementation of a 16-bit 1-MS/s Calibration-Free SAR ADC Vic Tian
104 Design and Implementation of 12-bit Sub-ranged SAR ADCs Rih, Wei-Shu
104 Design and Implementation of 8-bit Ultra-High-Speed SAR ADCs Chang, Che-Wei
103 Design and Implementation of 2b/Cycle-Based 10-bit High-Speed SAR ADCs (Graduated, FocalTech) Tseng, Hua-Wei
103 Design of a Timing Skew Calibration Processor for High-Speed Time-Interleaved ADCs (Graduated, Realtek) Hu, Chia-Yi
103 A 12-bit 100-MS/s Sub-Ranged SAR ADC with a Binary-Window DAC Switching (Graduated, Elite Tech) Hsu, Ya-Mien
103 A 14-bit Analog-to-Digital Converter with Background Nonlinearity Calibration Technique (Graduated, ALi Tech) Andrew Lee
103 Design and Implementation of 12-bit SAR ADCs with Binary-Window DAC Switching Technique (Graduated) Paul Ni
102 Design and Implementation of an 8-bit 1.25-GS/s Subranged-SAR ADC (Graduated, FocalTech) Tsai, Cheng-Hsun
102 Design and Implementation of a 12-bit 100-MS/s SAR ADC (Graduated, Faraday Tech.) Yen, Chia-Wei
102 Low-Power SAR ADC Design using Capacitor-Swapping Techniques (Graduated, ICL/ITRI) Shih, Song-You
102 Design and Implementation of a 10-bit 160-MS/s SAR ADC (Graduated, UMC) Yeh, Hsuan-Chih
Academic Year Project Title Student
110 Biomedical Analog Front-End Circuits 王昱晴、劉晴華
110 Temperature Sensing and Conversion Circuits 簡瑞智、張上為
110 CMOS Bandgap Voltage Reference 游心慈
109 A 150 nW CMOS Temperature Sensor 侯宏諭、張聖群
109 An 11-nW CMOS Temperature-to-Digital Converter 江雅茹、紀宏憲
109 A Fully-Integrated 71 nW CMOS Temperature Sensor 倪隆靖、呂永玄
109 A Class-AB Amplifier With −101 dB THD+N 陳冠余、蕭瑜葶
109 A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference 王昱翔、施佳鳳
108 A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time 陳品豪、吳昇翰
108 Capacitorless Self-Clocked All-Digital Low-Dropout Regulator 余心豪、賴冠衡
108 Switched Capacitor based High Positive and Negative Voltage Charge-pump 林賢順、蔡旻修、何宗翰
107 Bandgap Reference Circuits: Group-2 謝昱廷,莊懿
107 Bandgap Reference Circuits: Group-1 林惟鍾,林巨彥
107 Analog and digital circuit implementation 王挺安、蕭靖燁
106 Bandgap Reference and Regulators 周郁桀、邵丞擇、馬世為
105 A 10-bit 100-KS/s SAR ADC 賴冠亨、李榮章
105 A biomedical analog front-end (AFE) circuit: IA + PGA 邱宥榮、游景賀
105 A LDO regulator for biomedical AFE circuits 曾俊銘、江振忠
105 A bandgap circuit design 葉建祖
105 An analog front-end (receiver) circuits for logic analyzers (LAs) 洪宇廷
104 A 10-bit 100-MS/s SAR ADC 池振聖、侯人文
104 A 10-bit 1-MS/s SAR ADC 胡家瑋、朱致緯
104 Bandgap Reference Circuits 簡國訓、黃林育麟
104 ADC and IA Testing 林道、黃金增
103 Energy Harvesting System Design 黃揚景、林鈺翔
103 Biomedical Sensing System Design 唐煜杰、劉建宏
103 High-Speed Instrumentation AFE Circuit Design 鄧逸祥
102 Biomedical Analog Front-End Circuit Design 洪瑋謙, 張振誠
102 12-bit Digital-to-Analog Conversion Circuit Design David Yang
101 Biomedical Sensing System Design 孫以諾,謝曜竹,任欣圻
Year Deeds
2021 109學年度 電子系專題競賽 優勝 (學生: 王昱翔、施佳鳳)
2019 奇景盃IC佈局競賽 佳作 (學生: 周棋緯、謝昱廷)
2019 108學年度 電子系專題競賽 優勝 (學生: 余心豪、郭建鋒)
2018 107學年度 電子系專題競賽 優勝 (學生: 林惟鍾、莊懿)
2017 ISOCC 2017, Best Paper Award (Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih)